323 #define LANE_REG(lane, offset)			(0x400 * (lane) + (offset))  argument
709 					   u8 lane)  in rockchip_hdptx_phy_set_voltage()  argument
716 			ctrl = &tx_drv_ctrl_rbr_dp_mode[dp->voltage[lane]][dp->pre[lane]];  in rockchip_hdptx_phy_set_voltage()
718 			ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]];  in rockchip_hdptx_phy_set_voltage()
719 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),  in rockchip_hdptx_phy_set_voltage()
722 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c28),  in rockchip_hdptx_phy_set_voltage()
725 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c30),  in rockchip_hdptx_phy_set_voltage()
731 		ctrl = &tx_drv_ctrl_r216_r243[dp->voltage[lane]][dp->pre[lane]];  in rockchip_hdptx_phy_set_voltage()
732 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),  in rockchip_hdptx_phy_set_voltage()
735 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c),  in rockchip_hdptx_phy_set_voltage()
738 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34),  in rockchip_hdptx_phy_set_voltage()
744 			ctrl = &tx_drv_ctrl_hbr_dp_mode[dp->voltage[lane]][dp->pre[lane]];  in rockchip_hdptx_phy_set_voltage()
746 			ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]];  in rockchip_hdptx_phy_set_voltage()
747 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),  in rockchip_hdptx_phy_set_voltage()
750 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c),  in rockchip_hdptx_phy_set_voltage()
753 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34),  in rockchip_hdptx_phy_set_voltage()
758 		ctrl = &tx_drv_ctrl_r324[dp->voltage[lane]][dp->pre[lane]];  in rockchip_hdptx_phy_set_voltage()
759 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),  in rockchip_hdptx_phy_set_voltage()
762 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c),  in rockchip_hdptx_phy_set_voltage()
765 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34),  in rockchip_hdptx_phy_set_voltage()
770 		ctrl = &tx_drv_ctrl_r432[dp->voltage[lane]][dp->pre[lane]];  in rockchip_hdptx_phy_set_voltage()
771 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),  in rockchip_hdptx_phy_set_voltage()
774 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c),  in rockchip_hdptx_phy_set_voltage()
777 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34),  in rockchip_hdptx_phy_set_voltage()
783 		ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]];  in rockchip_hdptx_phy_set_voltage()
784 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),  in rockchip_hdptx_phy_set_voltage()
787 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c),  in rockchip_hdptx_phy_set_voltage()
790 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34),  in rockchip_hdptx_phy_set_voltage()
796 	regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c0c),  in rockchip_hdptx_phy_set_voltage()
801 	regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c10),  in rockchip_hdptx_phy_set_voltage()
807 	regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c14),  in rockchip_hdptx_phy_set_voltage()
813 	regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c18),  in rockchip_hdptx_phy_set_voltage()
823 	regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c1c),  in rockchip_hdptx_phy_set_voltage()
829 	regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c28),  in rockchip_hdptx_phy_set_voltage()
832 	regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c6c),  in rockchip_hdptx_phy_set_voltage()
835 	regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c58),  in rockchip_hdptx_phy_set_voltage()
838 	regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c40),  in rockchip_hdptx_phy_set_voltage()
846 	u8 lane;  in rockchip_hdptx_phy_set_voltages()  local
850 	for (lane = 0; lane < dp->lanes; lane++)  in rockchip_hdptx_phy_set_voltages()
851 		rockchip_hdptx_phy_set_voltage(hdptx, dp, lane);  in rockchip_hdptx_phy_set_voltages()
1300 	u32 lane;  in rockchip_hdptx_phy_reset()  local
1310 	for (lane = 0; lane < 4; lane++)  in rockchip_hdptx_phy_reset()
1311 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c04),  in rockchip_hdptx_phy_reset()
1328 	u32 lane;  in rockchip_hdptx_phy_power_on()  local
1332 	for (lane = 0; lane < 4; lane++) {  in rockchip_hdptx_phy_power_on()
1333 		u32 invert = hdptx->lane_polarity_invert[lane];  in rockchip_hdptx_phy_power_on()
1335 		regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c78),  in rockchip_hdptx_phy_power_on()