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Searched refs:gate (Results 1 – 25 of 51) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/dts/
H A Dsocfpga.dtsi289 compatible = "altr,socfpga-gate-clk";
291 clk-gate = <0x60 0>;
303 compatible = "altr,socfpga-gate-clk";
306 clk-gate = <0x60 1>;
311 compatible = "altr,socfpga-gate-clk";
318 compatible = "altr,socfpga-gate-clk";
321 clk-gate = <0x60 2>;
326 compatible = "altr,socfpga-gate-clk";
329 clk-gate = <0x60 3>;
334 compatible = "altr,socfpga-gate-clk";
[all …]
H A Domap36xx-clocks.dtsi20 compatible = "ti,hsdiv-gate-clock";
30 compatible = "ti,hsdiv-gate-clock";
39 compatible = "ti,hsdiv-gate-clock";
48 compatible = "ti,hsdiv-gate-clock";
57 compatible = "ti,hsdiv-gate-clock";
66 compatible = "ti,wait-gate-clock";
H A Domap3xxx-clocks.dtsi36 compatible = "ti,gate-clock";
222 compatible = "ti,gate-clock";
264 compatible = "ti,gate-clock";
379 compatible = "ti,gate-clock";
438 compatible = "ti,gate-clock";
466 compatible = "ti,gate-clock";
494 compatible = "ti,gate-clock";
511 compatible = "ti,composite-no-wait-gate-clock";
595 compatible = "ti,composite-gate-clock";
617 compatible = "ti,composite-gate-clock";
[all …]
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi48 compatible = "ti,composite-gate-clock";
109 compatible = "ti,wait-gate-clock";
117 compatible = "ti,gate-clock";
125 compatible = "ti,gate-clock";
133 compatible = "ti,wait-gate-clock";
157 compatible = "ti,wait-gate-clock";
165 compatible = "ti,dss-gate-clock";
182 compatible = "ti,gate-clock";
190 compatible = "ti,dss-gate-clock";
H A Dam33xx-clocks.dtsi101 compatible = "ti,gate-clock";
109 compatible = "ti,gate-clock";
117 compatible = "ti,gate-clock";
224 compatible = "ti,am3-dpll-no-gate-clock";
248 compatible = "ti,am3-dpll-no-gate-clock";
265 compatible = "ti,am3-dpll-no-gate-j-type-clock";
297 compatible = "ti,gate-clock";
321 compatible = "ti,gate-clock";
344 compatible = "ti,gate-clock";
401 compatible = "ti,gate-clock";
[all …]
H A Dam43xx-clocks.dtsi109 compatible = "ti,gate-clock";
117 compatible = "ti,gate-clock";
125 compatible = "ti,gate-clock";
133 compatible = "ti,gate-clock";
141 compatible = "ti,gate-clock";
149 compatible = "ti,gate-clock";
351 compatible = "ti,gate-clock";
504 compatible = "ti,gate-clock";
512 compatible = "ti,gate-clock";
520 compatible = "ti,gate-clock";
[all …]
H A Dsocfpga_arria10.dtsi347 compatible = "altr,socfpga-a10-gate-clk";
350 clk-gate = <0x48 1>;
355 compatible = "altr,socfpga-a10-gate-clk";
358 clk-gate = <0x48 2>;
363 compatible = "altr,socfpga-a10-gate-clk";
366 clk-gate = <0x48 3>;
371 compatible = "altr,socfpga-a10-gate-clk";
374 clk-gate = <0x48 0>;
379 compatible = "altr,socfpga-a10-gate-clk";
381 clk-gate = <0xC8 5>;
[all …]
H A Domap34xx-omap36xx-clocks.dtsi53 compatible = "ti,gate-clock";
70 compatible = "ti,gate-clock";
134 compatible = "ti,wait-gate-clock";
142 compatible = "ti,wait-gate-clock";
187 compatible = "ti,wait-gate-clock";
219 compatible = "ti,wait-gate-clock";
H A Ddra7xx-clocks.dtsi1178 compatible = "ti,gate-clock";
1243 compatible = "ti,gate-clock";
1251 compatible = "ti,gate-clock";
1269 compatible = "ti,gate-clock";
1277 compatible = "ti,gate-clock";
1285 compatible = "ti,gate-clock";
1293 compatible = "ti,gate-clock";
1514 compatible = "ti,gate-clock";
1522 compatible = "ti,gate-clock";
1530 compatible = "ti,gate-clock";
[all …]
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Drockchip.txt12 The gate registers form a continuos block which makes the dt node
14 one gate clock spanning all registers or they can be divided into
19 - compatible : "rockchip,rk2928-gate-clk"
22 - clock-output-names : the corresponding gate names that the clock controls
23 - clocks : should contain the parent clock for each individual gate,
27 Example using multiple gate clocks:
29 clk_gates0: gate-clk@200000d0 {
30 compatible = "rockchip,rk2928-gate-clk";
54 clk_gates1: gate-clk@200000d4 {
55 compatible = "rockchip,rk2928-gate-clk";
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.h96 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) argument
97 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) argument
98 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) argument
99 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) argument
100 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) argument
101 #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) argument
103 #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) argument
391 struct bcm_clk_gate gate; member
395 struct bcm_clk_gate gate; member
399 struct bcm_clk_gate gate; member
H A Dclk-bcm281xx.c132 .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
136 .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
140 .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
145 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
157 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
169 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
181 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
194 .gate = SW_ONLY_GATE(0x0358, 20, 4),
199 .gate = SW_ONLY_GATE(0x035c, 20, 4),
204 .gate = SW_ONLY_GATE(0x0364, 20, 4),
[all …]
H A Dclk-core.c84 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable() local
106 if (gate_exists(gate)) { in peri_clk_enable()
107 reg = readl(base + cd->gate.offset); in peri_clk_enable()
108 reg |= (1 << cd->gate.en_bit); in peri_clk_enable()
109 writel(reg, base + cd->gate.offset); in peri_clk_enable()
139 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); in peri_clk_enable()
146 reg = readl(base + cd->gate.offset); in peri_clk_enable()
147 reg &= ~(1 << cd->gate.en_bit); in peri_clk_enable()
148 writel(reg, base + cd->gate.offset); in peri_clk_enable()
151 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); in peri_clk_enable()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.h96 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) argument
97 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) argument
98 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) argument
99 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) argument
100 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) argument
101 #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) argument
103 #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) argument
391 struct bcm_clk_gate gate; member
395 struct bcm_clk_gate gate; member
399 struct bcm_clk_gate gate; member
H A Dclk-bcm235xx.c132 .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
136 .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
140 .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
145 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
157 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
169 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
181 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
194 .gate = SW_ONLY_GATE(0x0358, 20, 4),
199 .gate = SW_ONLY_GATE(0x035c, 20, 4),
204 .gate = SW_ONLY_GATE(0x0364, 20, 4),
[all …]
H A Dclk-core.c84 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable() local
106 if (gate_exists(gate)) { in peri_clk_enable()
107 reg = readl(base + cd->gate.offset); in peri_clk_enable()
108 reg |= (1 << cd->gate.en_bit); in peri_clk_enable()
109 writel(reg, base + cd->gate.offset); in peri_clk_enable()
139 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); in peri_clk_enable()
146 reg = readl(base + cd->gate.offset); in peri_clk_enable()
147 reg &= ~(1 << cd->gate.en_bit); in peri_clk_enable()
148 writel(reg, base + cd->gate.offset); in peri_clk_enable()
151 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); in peri_clk_enable()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx7ulp/
H A Dscg.c172 u32 shift, mask, gate, valid; in scg_apll_pfd_get_rate() local
176 gate = SCG_PLL_PFD0_GATE_MASK; in scg_apll_pfd_get_rate()
182 gate = SCG_PLL_PFD1_GATE_MASK; in scg_apll_pfd_get_rate()
188 gate = SCG_PLL_PFD2_GATE_MASK; in scg_apll_pfd_get_rate()
194 gate = SCG_PLL_PFD3_GATE_MASK; in scg_apll_pfd_get_rate()
204 if (reg & gate || !(reg & valid)) in scg_apll_pfd_get_rate()
222 u32 shift, mask, gate, valid; in scg_spll_pfd_get_rate() local
226 gate = SCG_PLL_PFD0_GATE_MASK; in scg_spll_pfd_get_rate()
232 gate = SCG_PLL_PFD1_GATE_MASK; in scg_spll_pfd_get_rate()
238 gate = SCG_PLL_PFD2_GATE_MASK; in scg_spll_pfd_get_rate()
[all …]
/rk3399_rockchip-uboot/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c21 .gate = uniphier_pxs2_sys_clk_gate,
33 .gate = uniphier_ld20_sys_clk_gate,
H A Dclk-uniphier.h31 const struct uniphier_clk_gate_data *gate; member
H A Dclk-uniphier-mio.c81 .gate = uniphier_mio_clk_gate,
/rk3399_rockchip-uboot/arch/arm/mach-imx/
H A Drdc-sema.c67 &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_lock()
68 reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_lock()
95 reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_unlock()
99 writeb(0x0, &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_unlock()
/rk3399_rockchip-uboot/board/aristainetos/
H A Dclocks2.cfg17 /* set the default clock gate to save power */
H A Dclocks.cfg17 /* set the default clock gate to save power */
/rk3399_rockchip-uboot/board/advantech/dms-ba16/
H A Dclocks.cfg1 /* set the default clock gate to save power */
/rk3399_rockchip-uboot/board/tqc/tqma6/
H A Dclocks.cfg11 /* set the default clock gate to save power */

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