151c580c6SStefan Roese/* 251c580c6SStefan Roese * Copyright (C) 2012 Altera <www.altera.com> 351c580c6SStefan Roese * 45bf1f1edSStefan Roese * SPDX-License-Identifier: GPL-2.0+ 551c580c6SStefan Roese */ 651c580c6SStefan Roese 751c580c6SStefan Roese#include "skeleton.dtsi" 851c580c6SStefan Roese#include <dt-bindings/reset/altr,rst-mgr.h> 951c580c6SStefan Roese 1051c580c6SStefan Roese/ { 1151c580c6SStefan Roese #address-cells = <1>; 1251c580c6SStefan Roese #size-cells = <1>; 1351c580c6SStefan Roese 1451c580c6SStefan Roese aliases { 1551c580c6SStefan Roese ethernet0 = &gmac0; 1651c580c6SStefan Roese ethernet1 = &gmac1; 1751c580c6SStefan Roese serial0 = &uart0; 1851c580c6SStefan Roese serial1 = &uart1; 1951c580c6SStefan Roese timer0 = &timer0; 2051c580c6SStefan Roese timer1 = &timer1; 2151c580c6SStefan Roese timer2 = &timer2; 2251c580c6SStefan Roese timer3 = &timer3; 23b09b72d8SMarek Vasut spi0 = &qspi; 24b09b72d8SMarek Vasut spi1 = &spi0; 25b09b72d8SMarek Vasut spi2 = &spi1; 2651c580c6SStefan Roese }; 2751c580c6SStefan Roese 2851c580c6SStefan Roese cpus { 2951c580c6SStefan Roese #address-cells = <1>; 3051c580c6SStefan Roese #size-cells = <0>; 3151c580c6SStefan Roese 3251c580c6SStefan Roese cpu@0 { 3351c580c6SStefan Roese compatible = "arm,cortex-a9"; 3451c580c6SStefan Roese device_type = "cpu"; 3551c580c6SStefan Roese reg = <0>; 3651c580c6SStefan Roese next-level-cache = <&L2>; 3751c580c6SStefan Roese }; 3851c580c6SStefan Roese cpu@1 { 3951c580c6SStefan Roese compatible = "arm,cortex-a9"; 4051c580c6SStefan Roese device_type = "cpu"; 4151c580c6SStefan Roese reg = <1>; 4251c580c6SStefan Roese next-level-cache = <&L2>; 4351c580c6SStefan Roese }; 4451c580c6SStefan Roese }; 4551c580c6SStefan Roese 4651c580c6SStefan Roese intc: intc@fffed000 { 4751c580c6SStefan Roese compatible = "arm,cortex-a9-gic"; 4851c580c6SStefan Roese #interrupt-cells = <3>; 4951c580c6SStefan Roese interrupt-controller; 5051c580c6SStefan Roese reg = <0xfffed000 0x1000>, 5151c580c6SStefan Roese <0xfffec100 0x100>; 5251c580c6SStefan Roese }; 5351c580c6SStefan Roese 5451c580c6SStefan Roese soc { 5551c580c6SStefan Roese #address-cells = <1>; 5651c580c6SStefan Roese #size-cells = <1>; 5751c580c6SStefan Roese compatible = "simple-bus"; 5851c580c6SStefan Roese device_type = "soc"; 5951c580c6SStefan Roese interrupt-parent = <&intc>; 6051c580c6SStefan Roese ranges; 6151c580c6SStefan Roese 6251c580c6SStefan Roese amba { 6351c580c6SStefan Roese compatible = "arm,amba-bus"; 6451c580c6SStefan Roese #address-cells = <1>; 6551c580c6SStefan Roese #size-cells = <1>; 6651c580c6SStefan Roese ranges; 6751c580c6SStefan Roese 6851c580c6SStefan Roese pdma: pdma@ffe01000 { 6951c580c6SStefan Roese compatible = "arm,pl330", "arm,primecell"; 7051c580c6SStefan Roese reg = <0xffe01000 0x1000>; 7151c580c6SStefan Roese interrupts = <0 104 4>, 7251c580c6SStefan Roese <0 105 4>, 7351c580c6SStefan Roese <0 106 4>, 7451c580c6SStefan Roese <0 107 4>, 7551c580c6SStefan Roese <0 108 4>, 7651c580c6SStefan Roese <0 109 4>, 7751c580c6SStefan Roese <0 110 4>, 7851c580c6SStefan Roese <0 111 4>; 7951c580c6SStefan Roese #dma-cells = <1>; 8051c580c6SStefan Roese #dma-channels = <8>; 8151c580c6SStefan Roese #dma-requests = <32>; 8251c580c6SStefan Roese clocks = <&l4_main_clk>; 8351c580c6SStefan Roese clock-names = "apb_pclk"; 8451c580c6SStefan Roese }; 8551c580c6SStefan Roese }; 8651c580c6SStefan Roese 8751c580c6SStefan Roese can0: can@ffc00000 { 8851c580c6SStefan Roese compatible = "bosch,d_can"; 8951c580c6SStefan Roese reg = <0xffc00000 0x1000>; 9051c580c6SStefan Roese interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; 9151c580c6SStefan Roese clocks = <&can0_clk>; 9251c580c6SStefan Roese status = "disabled"; 9351c580c6SStefan Roese }; 9451c580c6SStefan Roese 9551c580c6SStefan Roese can1: can@ffc01000 { 9651c580c6SStefan Roese compatible = "bosch,d_can"; 9751c580c6SStefan Roese reg = <0xffc01000 0x1000>; 9851c580c6SStefan Roese interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; 9951c580c6SStefan Roese clocks = <&can1_clk>; 10051c580c6SStefan Roese status = "disabled"; 10151c580c6SStefan Roese }; 10251c580c6SStefan Roese 10351c580c6SStefan Roese clkmgr@ffd04000 { 10451c580c6SStefan Roese compatible = "altr,clk-mgr"; 10551c580c6SStefan Roese reg = <0xffd04000 0x1000>; 10651c580c6SStefan Roese 10751c580c6SStefan Roese clocks { 10851c580c6SStefan Roese #address-cells = <1>; 10951c580c6SStefan Roese #size-cells = <0>; 11051c580c6SStefan Roese 11151c580c6SStefan Roese osc1: osc1 { 11251c580c6SStefan Roese #clock-cells = <0>; 11351c580c6SStefan Roese compatible = "fixed-clock"; 11451c580c6SStefan Roese }; 11551c580c6SStefan Roese 11651c580c6SStefan Roese osc2: osc2 { 11751c580c6SStefan Roese #clock-cells = <0>; 11851c580c6SStefan Roese compatible = "fixed-clock"; 11951c580c6SStefan Roese }; 12051c580c6SStefan Roese 12151c580c6SStefan Roese f2s_periph_ref_clk: f2s_periph_ref_clk { 12251c580c6SStefan Roese #clock-cells = <0>; 12351c580c6SStefan Roese compatible = "fixed-clock"; 12451c580c6SStefan Roese }; 12551c580c6SStefan Roese 12651c580c6SStefan Roese f2s_sdram_ref_clk: f2s_sdram_ref_clk { 12751c580c6SStefan Roese #clock-cells = <0>; 12851c580c6SStefan Roese compatible = "fixed-clock"; 12951c580c6SStefan Roese }; 13051c580c6SStefan Roese 13151c580c6SStefan Roese main_pll: main_pll { 13251c580c6SStefan Roese #address-cells = <1>; 13351c580c6SStefan Roese #size-cells = <0>; 13451c580c6SStefan Roese #clock-cells = <0>; 13551c580c6SStefan Roese compatible = "altr,socfpga-pll-clock"; 13651c580c6SStefan Roese clocks = <&osc1>; 13751c580c6SStefan Roese reg = <0x40>; 13851c580c6SStefan Roese 13951c580c6SStefan Roese mpuclk: mpuclk { 14051c580c6SStefan Roese #clock-cells = <0>; 14151c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 14251c580c6SStefan Roese clocks = <&main_pll>; 14351c580c6SStefan Roese div-reg = <0xe0 0 9>; 14451c580c6SStefan Roese reg = <0x48>; 14551c580c6SStefan Roese }; 14651c580c6SStefan Roese 14751c580c6SStefan Roese mainclk: mainclk { 14851c580c6SStefan Roese #clock-cells = <0>; 14951c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 15051c580c6SStefan Roese clocks = <&main_pll>; 15151c580c6SStefan Roese div-reg = <0xe4 0 9>; 15251c580c6SStefan Roese reg = <0x4C>; 15351c580c6SStefan Roese }; 15451c580c6SStefan Roese 15551c580c6SStefan Roese dbg_base_clk: dbg_base_clk { 15651c580c6SStefan Roese #clock-cells = <0>; 15751c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 15851c580c6SStefan Roese clocks = <&main_pll>; 15951c580c6SStefan Roese div-reg = <0xe8 0 9>; 16051c580c6SStefan Roese reg = <0x50>; 16151c580c6SStefan Roese }; 16251c580c6SStefan Roese 16351c580c6SStefan Roese main_qspi_clk: main_qspi_clk { 16451c580c6SStefan Roese #clock-cells = <0>; 16551c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 16651c580c6SStefan Roese clocks = <&main_pll>; 16751c580c6SStefan Roese reg = <0x54>; 16851c580c6SStefan Roese }; 16951c580c6SStefan Roese 17051c580c6SStefan Roese main_nand_sdmmc_clk: main_nand_sdmmc_clk { 17151c580c6SStefan Roese #clock-cells = <0>; 17251c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 17351c580c6SStefan Roese clocks = <&main_pll>; 17451c580c6SStefan Roese reg = <0x58>; 17551c580c6SStefan Roese }; 17651c580c6SStefan Roese 17751c580c6SStefan Roese cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { 17851c580c6SStefan Roese #clock-cells = <0>; 17951c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 18051c580c6SStefan Roese clocks = <&main_pll>; 18151c580c6SStefan Roese reg = <0x5C>; 18251c580c6SStefan Roese }; 18351c580c6SStefan Roese }; 18451c580c6SStefan Roese 18551c580c6SStefan Roese periph_pll: periph_pll { 18651c580c6SStefan Roese #address-cells = <1>; 18751c580c6SStefan Roese #size-cells = <0>; 18851c580c6SStefan Roese #clock-cells = <0>; 18951c580c6SStefan Roese compatible = "altr,socfpga-pll-clock"; 19051c580c6SStefan Roese clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; 19151c580c6SStefan Roese reg = <0x80>; 19251c580c6SStefan Roese 19351c580c6SStefan Roese emac0_clk: emac0_clk { 19451c580c6SStefan Roese #clock-cells = <0>; 19551c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 19651c580c6SStefan Roese clocks = <&periph_pll>; 19751c580c6SStefan Roese reg = <0x88>; 19851c580c6SStefan Roese }; 19951c580c6SStefan Roese 20051c580c6SStefan Roese emac1_clk: emac1_clk { 20151c580c6SStefan Roese #clock-cells = <0>; 20251c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 20351c580c6SStefan Roese clocks = <&periph_pll>; 20451c580c6SStefan Roese reg = <0x8C>; 20551c580c6SStefan Roese }; 20651c580c6SStefan Roese 20751c580c6SStefan Roese per_qspi_clk: per_qsi_clk { 20851c580c6SStefan Roese #clock-cells = <0>; 20951c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 21051c580c6SStefan Roese clocks = <&periph_pll>; 21151c580c6SStefan Roese reg = <0x90>; 21251c580c6SStefan Roese }; 21351c580c6SStefan Roese 21451c580c6SStefan Roese per_nand_mmc_clk: per_nand_mmc_clk { 21551c580c6SStefan Roese #clock-cells = <0>; 21651c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 21751c580c6SStefan Roese clocks = <&periph_pll>; 21851c580c6SStefan Roese reg = <0x94>; 21951c580c6SStefan Roese }; 22051c580c6SStefan Roese 22151c580c6SStefan Roese per_base_clk: per_base_clk { 22251c580c6SStefan Roese #clock-cells = <0>; 22351c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 22451c580c6SStefan Roese clocks = <&periph_pll>; 22551c580c6SStefan Roese reg = <0x98>; 22651c580c6SStefan Roese }; 22751c580c6SStefan Roese 22851c580c6SStefan Roese h2f_usr1_clk: h2f_usr1_clk { 22951c580c6SStefan Roese #clock-cells = <0>; 23051c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 23151c580c6SStefan Roese clocks = <&periph_pll>; 23251c580c6SStefan Roese reg = <0x9C>; 23351c580c6SStefan Roese }; 23451c580c6SStefan Roese }; 23551c580c6SStefan Roese 23651c580c6SStefan Roese sdram_pll: sdram_pll { 23751c580c6SStefan Roese #address-cells = <1>; 23851c580c6SStefan Roese #size-cells = <0>; 23951c580c6SStefan Roese #clock-cells = <0>; 24051c580c6SStefan Roese compatible = "altr,socfpga-pll-clock"; 24151c580c6SStefan Roese clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; 24251c580c6SStefan Roese reg = <0xC0>; 24351c580c6SStefan Roese 24451c580c6SStefan Roese ddr_dqs_clk: ddr_dqs_clk { 24551c580c6SStefan Roese #clock-cells = <0>; 24651c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 24751c580c6SStefan Roese clocks = <&sdram_pll>; 24851c580c6SStefan Roese reg = <0xC8>; 24951c580c6SStefan Roese }; 25051c580c6SStefan Roese 25151c580c6SStefan Roese ddr_2x_dqs_clk: ddr_2x_dqs_clk { 25251c580c6SStefan Roese #clock-cells = <0>; 25351c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 25451c580c6SStefan Roese clocks = <&sdram_pll>; 25551c580c6SStefan Roese reg = <0xCC>; 25651c580c6SStefan Roese }; 25751c580c6SStefan Roese 25851c580c6SStefan Roese ddr_dq_clk: ddr_dq_clk { 25951c580c6SStefan Roese #clock-cells = <0>; 26051c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 26151c580c6SStefan Roese clocks = <&sdram_pll>; 26251c580c6SStefan Roese reg = <0xD0>; 26351c580c6SStefan Roese }; 26451c580c6SStefan Roese 26551c580c6SStefan Roese h2f_usr2_clk: h2f_usr2_clk { 26651c580c6SStefan Roese #clock-cells = <0>; 26751c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 26851c580c6SStefan Roese clocks = <&sdram_pll>; 26951c580c6SStefan Roese reg = <0xD4>; 27051c580c6SStefan Roese }; 27151c580c6SStefan Roese }; 27251c580c6SStefan Roese 27351c580c6SStefan Roese mpu_periph_clk: mpu_periph_clk { 27451c580c6SStefan Roese #clock-cells = <0>; 27551c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 27651c580c6SStefan Roese clocks = <&mpuclk>; 27751c580c6SStefan Roese fixed-divider = <4>; 27851c580c6SStefan Roese }; 27951c580c6SStefan Roese 28051c580c6SStefan Roese mpu_l2_ram_clk: mpu_l2_ram_clk { 28151c580c6SStefan Roese #clock-cells = <0>; 28251c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 28351c580c6SStefan Roese clocks = <&mpuclk>; 28451c580c6SStefan Roese fixed-divider = <2>; 28551c580c6SStefan Roese }; 28651c580c6SStefan Roese 28751c580c6SStefan Roese l4_main_clk: l4_main_clk { 28851c580c6SStefan Roese #clock-cells = <0>; 28951c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 29051c580c6SStefan Roese clocks = <&mainclk>; 29151c580c6SStefan Roese clk-gate = <0x60 0>; 29251c580c6SStefan Roese }; 29351c580c6SStefan Roese 29451c580c6SStefan Roese l3_main_clk: l3_main_clk { 29551c580c6SStefan Roese #clock-cells = <0>; 29651c580c6SStefan Roese compatible = "altr,socfpga-perip-clk"; 29751c580c6SStefan Roese clocks = <&mainclk>; 29851c580c6SStefan Roese fixed-divider = <1>; 29951c580c6SStefan Roese }; 30051c580c6SStefan Roese 30151c580c6SStefan Roese l3_mp_clk: l3_mp_clk { 30251c580c6SStefan Roese #clock-cells = <0>; 30351c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 30451c580c6SStefan Roese clocks = <&mainclk>; 30551c580c6SStefan Roese div-reg = <0x64 0 2>; 30651c580c6SStefan Roese clk-gate = <0x60 1>; 30751c580c6SStefan Roese }; 30851c580c6SStefan Roese 30951c580c6SStefan Roese l3_sp_clk: l3_sp_clk { 31051c580c6SStefan Roese #clock-cells = <0>; 31151c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 31251c580c6SStefan Roese clocks = <&mainclk>; 31351c580c6SStefan Roese div-reg = <0x64 2 2>; 31451c580c6SStefan Roese }; 31551c580c6SStefan Roese 31651c580c6SStefan Roese l4_mp_clk: l4_mp_clk { 31751c580c6SStefan Roese #clock-cells = <0>; 31851c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 31951c580c6SStefan Roese clocks = <&mainclk>, <&per_base_clk>; 32051c580c6SStefan Roese div-reg = <0x64 4 3>; 32151c580c6SStefan Roese clk-gate = <0x60 2>; 32251c580c6SStefan Roese }; 32351c580c6SStefan Roese 32451c580c6SStefan Roese l4_sp_clk: l4_sp_clk { 32551c580c6SStefan Roese #clock-cells = <0>; 32651c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 32751c580c6SStefan Roese clocks = <&mainclk>, <&per_base_clk>; 32851c580c6SStefan Roese div-reg = <0x64 7 3>; 32951c580c6SStefan Roese clk-gate = <0x60 3>; 33051c580c6SStefan Roese }; 33151c580c6SStefan Roese 33251c580c6SStefan Roese dbg_at_clk: dbg_at_clk { 33351c580c6SStefan Roese #clock-cells = <0>; 33451c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 33551c580c6SStefan Roese clocks = <&dbg_base_clk>; 33651c580c6SStefan Roese div-reg = <0x68 0 2>; 33751c580c6SStefan Roese clk-gate = <0x60 4>; 33851c580c6SStefan Roese }; 33951c580c6SStefan Roese 34051c580c6SStefan Roese dbg_clk: dbg_clk { 34151c580c6SStefan Roese #clock-cells = <0>; 34251c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 34351c580c6SStefan Roese clocks = <&dbg_base_clk>; 34451c580c6SStefan Roese div-reg = <0x68 2 2>; 34551c580c6SStefan Roese clk-gate = <0x60 5>; 34651c580c6SStefan Roese }; 34751c580c6SStefan Roese 34851c580c6SStefan Roese dbg_trace_clk: dbg_trace_clk { 34951c580c6SStefan Roese #clock-cells = <0>; 35051c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 35151c580c6SStefan Roese clocks = <&dbg_base_clk>; 35251c580c6SStefan Roese div-reg = <0x6C 0 3>; 35351c580c6SStefan Roese clk-gate = <0x60 6>; 35451c580c6SStefan Roese }; 35551c580c6SStefan Roese 35651c580c6SStefan Roese dbg_timer_clk: dbg_timer_clk { 35751c580c6SStefan Roese #clock-cells = <0>; 35851c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 35951c580c6SStefan Roese clocks = <&dbg_base_clk>; 36051c580c6SStefan Roese clk-gate = <0x60 7>; 36151c580c6SStefan Roese }; 36251c580c6SStefan Roese 36351c580c6SStefan Roese cfg_clk: cfg_clk { 36451c580c6SStefan Roese #clock-cells = <0>; 36551c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 36651c580c6SStefan Roese clocks = <&cfg_h2f_usr0_clk>; 36751c580c6SStefan Roese clk-gate = <0x60 8>; 36851c580c6SStefan Roese }; 36951c580c6SStefan Roese 37051c580c6SStefan Roese h2f_user0_clk: h2f_user0_clk { 37151c580c6SStefan Roese #clock-cells = <0>; 37251c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 37351c580c6SStefan Roese clocks = <&cfg_h2f_usr0_clk>; 37451c580c6SStefan Roese clk-gate = <0x60 9>; 37551c580c6SStefan Roese }; 37651c580c6SStefan Roese 37751c580c6SStefan Roese emac_0_clk: emac_0_clk { 37851c580c6SStefan Roese #clock-cells = <0>; 37951c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 38051c580c6SStefan Roese clocks = <&emac0_clk>; 38151c580c6SStefan Roese clk-gate = <0xa0 0>; 38251c580c6SStefan Roese }; 38351c580c6SStefan Roese 38451c580c6SStefan Roese emac_1_clk: emac_1_clk { 38551c580c6SStefan Roese #clock-cells = <0>; 38651c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 38751c580c6SStefan Roese clocks = <&emac1_clk>; 38851c580c6SStefan Roese clk-gate = <0xa0 1>; 38951c580c6SStefan Roese }; 39051c580c6SStefan Roese 39151c580c6SStefan Roese usb_mp_clk: usb_mp_clk { 39251c580c6SStefan Roese #clock-cells = <0>; 39351c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 39451c580c6SStefan Roese clocks = <&per_base_clk>; 39551c580c6SStefan Roese clk-gate = <0xa0 2>; 39651c580c6SStefan Roese div-reg = <0xa4 0 3>; 39751c580c6SStefan Roese }; 39851c580c6SStefan Roese 39951c580c6SStefan Roese spi_m_clk: spi_m_clk { 40051c580c6SStefan Roese #clock-cells = <0>; 40151c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 40251c580c6SStefan Roese clocks = <&per_base_clk>; 40351c580c6SStefan Roese clk-gate = <0xa0 3>; 40451c580c6SStefan Roese div-reg = <0xa4 3 3>; 40551c580c6SStefan Roese }; 40651c580c6SStefan Roese 40751c580c6SStefan Roese can0_clk: can0_clk { 40851c580c6SStefan Roese #clock-cells = <0>; 40951c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 41051c580c6SStefan Roese clocks = <&per_base_clk>; 41151c580c6SStefan Roese clk-gate = <0xa0 4>; 41251c580c6SStefan Roese div-reg = <0xa4 6 3>; 41351c580c6SStefan Roese }; 41451c580c6SStefan Roese 41551c580c6SStefan Roese can1_clk: can1_clk { 41651c580c6SStefan Roese #clock-cells = <0>; 41751c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 41851c580c6SStefan Roese clocks = <&per_base_clk>; 41951c580c6SStefan Roese clk-gate = <0xa0 5>; 42051c580c6SStefan Roese div-reg = <0xa4 9 3>; 42151c580c6SStefan Roese }; 42251c580c6SStefan Roese 42351c580c6SStefan Roese gpio_db_clk: gpio_db_clk { 42451c580c6SStefan Roese #clock-cells = <0>; 42551c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 42651c580c6SStefan Roese clocks = <&per_base_clk>; 42751c580c6SStefan Roese clk-gate = <0xa0 6>; 42851c580c6SStefan Roese div-reg = <0xa8 0 24>; 42951c580c6SStefan Roese }; 43051c580c6SStefan Roese 43151c580c6SStefan Roese h2f_user1_clk: h2f_user1_clk { 43251c580c6SStefan Roese #clock-cells = <0>; 43351c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 43451c580c6SStefan Roese clocks = <&h2f_usr1_clk>; 43551c580c6SStefan Roese clk-gate = <0xa0 7>; 43651c580c6SStefan Roese }; 43751c580c6SStefan Roese 43851c580c6SStefan Roese sdmmc_clk: sdmmc_clk { 43951c580c6SStefan Roese #clock-cells = <0>; 44051c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 44151c580c6SStefan Roese clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 44251c580c6SStefan Roese clk-gate = <0xa0 8>; 44351c580c6SStefan Roese clk-phase = <0 135>; 44451c580c6SStefan Roese }; 44551c580c6SStefan Roese 44651c580c6SStefan Roese nand_x_clk: nand_x_clk { 44751c580c6SStefan Roese #clock-cells = <0>; 44851c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 44951c580c6SStefan Roese clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 45051c580c6SStefan Roese clk-gate = <0xa0 9>; 45151c580c6SStefan Roese }; 45251c580c6SStefan Roese 45351c580c6SStefan Roese nand_clk: nand_clk { 45451c580c6SStefan Roese #clock-cells = <0>; 45551c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 45651c580c6SStefan Roese clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 45751c580c6SStefan Roese clk-gate = <0xa0 10>; 45851c580c6SStefan Roese fixed-divider = <4>; 45951c580c6SStefan Roese }; 46051c580c6SStefan Roese 46151c580c6SStefan Roese qspi_clk: qspi_clk { 46251c580c6SStefan Roese #clock-cells = <0>; 46351c580c6SStefan Roese compatible = "altr,socfpga-gate-clk"; 46451c580c6SStefan Roese clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; 46551c580c6SStefan Roese clk-gate = <0xa0 11>; 46651c580c6SStefan Roese }; 46751c580c6SStefan Roese }; 46851c580c6SStefan Roese }; 46951c580c6SStefan Roese 47051c580c6SStefan Roese gmac0: ethernet@ff700000 { 47151c580c6SStefan Roese compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 47251c580c6SStefan Roese altr,sysmgr-syscon = <&sysmgr 0x60 0>; 47351c580c6SStefan Roese reg = <0xff700000 0x2000>; 47451c580c6SStefan Roese interrupts = <0 115 4>; 47551c580c6SStefan Roese interrupt-names = "macirq"; 47651c580c6SStefan Roese mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 47751c580c6SStefan Roese clocks = <&emac0_clk>; 47851c580c6SStefan Roese clock-names = "stmmaceth"; 47951c580c6SStefan Roese resets = <&rst EMAC0_RESET>; 48051c580c6SStefan Roese reset-names = "stmmaceth"; 48151c580c6SStefan Roese snps,multicast-filter-bins = <256>; 48251c580c6SStefan Roese snps,perfect-filter-entries = <128>; 48351c580c6SStefan Roese status = "disabled"; 48451c580c6SStefan Roese }; 48551c580c6SStefan Roese 48651c580c6SStefan Roese gmac1: ethernet@ff702000 { 48751c580c6SStefan Roese compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 48851c580c6SStefan Roese altr,sysmgr-syscon = <&sysmgr 0x60 2>; 48951c580c6SStefan Roese reg = <0xff702000 0x2000>; 49051c580c6SStefan Roese interrupts = <0 120 4>; 49151c580c6SStefan Roese interrupt-names = "macirq"; 49251c580c6SStefan Roese mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 49351c580c6SStefan Roese clocks = <&emac1_clk>; 49451c580c6SStefan Roese clock-names = "stmmaceth"; 49551c580c6SStefan Roese resets = <&rst EMAC1_RESET>; 49651c580c6SStefan Roese reset-names = "stmmaceth"; 49751c580c6SStefan Roese snps,multicast-filter-bins = <256>; 49851c580c6SStefan Roese snps,perfect-filter-entries = <128>; 49951c580c6SStefan Roese status = "disabled"; 50051c580c6SStefan Roese }; 50151c580c6SStefan Roese 50251c580c6SStefan Roese i2c0: i2c@ffc04000 { 50351c580c6SStefan Roese #address-cells = <1>; 50451c580c6SStefan Roese #size-cells = <0>; 50551c580c6SStefan Roese compatible = "snps,designware-i2c"; 50651c580c6SStefan Roese reg = <0xffc04000 0x1000>; 50751c580c6SStefan Roese clocks = <&l4_sp_clk>; 50851c580c6SStefan Roese interrupts = <0 158 0x4>; 50951c580c6SStefan Roese status = "disabled"; 51051c580c6SStefan Roese }; 51151c580c6SStefan Roese 51251c580c6SStefan Roese i2c1: i2c@ffc05000 { 51351c580c6SStefan Roese #address-cells = <1>; 51451c580c6SStefan Roese #size-cells = <0>; 51551c580c6SStefan Roese compatible = "snps,designware-i2c"; 51651c580c6SStefan Roese reg = <0xffc05000 0x1000>; 51751c580c6SStefan Roese clocks = <&l4_sp_clk>; 51851c580c6SStefan Roese interrupts = <0 159 0x4>; 51951c580c6SStefan Roese status = "disabled"; 52051c580c6SStefan Roese }; 52151c580c6SStefan Roese 52251c580c6SStefan Roese i2c2: i2c@ffc06000 { 52351c580c6SStefan Roese #address-cells = <1>; 52451c580c6SStefan Roese #size-cells = <0>; 52551c580c6SStefan Roese compatible = "snps,designware-i2c"; 52651c580c6SStefan Roese reg = <0xffc06000 0x1000>; 52751c580c6SStefan Roese clocks = <&l4_sp_clk>; 52851c580c6SStefan Roese interrupts = <0 160 0x4>; 52951c580c6SStefan Roese status = "disabled"; 53051c580c6SStefan Roese }; 53151c580c6SStefan Roese 53251c580c6SStefan Roese i2c3: i2c@ffc07000 { 53351c580c6SStefan Roese #address-cells = <1>; 53451c580c6SStefan Roese #size-cells = <0>; 53551c580c6SStefan Roese compatible = "snps,designware-i2c"; 53651c580c6SStefan Roese reg = <0xffc07000 0x1000>; 53751c580c6SStefan Roese clocks = <&l4_sp_clk>; 53851c580c6SStefan Roese interrupts = <0 161 0x4>; 53951c580c6SStefan Roese status = "disabled"; 54051c580c6SStefan Roese }; 54151c580c6SStefan Roese 54251c580c6SStefan Roese gpio0: gpio@ff708000 { 54351c580c6SStefan Roese #address-cells = <1>; 54451c580c6SStefan Roese #size-cells = <0>; 54551c580c6SStefan Roese compatible = "snps,dw-apb-gpio"; 54651c580c6SStefan Roese reg = <0xff708000 0x1000>; 54751c580c6SStefan Roese clocks = <&per_base_clk>; 54851c580c6SStefan Roese status = "disabled"; 54951c580c6SStefan Roese 55051c580c6SStefan Roese porta: gpio-controller@0 { 55151c580c6SStefan Roese compatible = "snps,dw-apb-gpio-port"; 552*660f53bcSMarek Vasut bank-name = "porta"; 55351c580c6SStefan Roese gpio-controller; 55451c580c6SStefan Roese #gpio-cells = <2>; 55551c580c6SStefan Roese snps,nr-gpios = <29>; 55651c580c6SStefan Roese reg = <0>; 55751c580c6SStefan Roese interrupt-controller; 55851c580c6SStefan Roese #interrupt-cells = <2>; 55951c580c6SStefan Roese interrupts = <0 164 4>; 56051c580c6SStefan Roese }; 56151c580c6SStefan Roese }; 56251c580c6SStefan Roese 56351c580c6SStefan Roese gpio1: gpio@ff709000 { 56451c580c6SStefan Roese #address-cells = <1>; 56551c580c6SStefan Roese #size-cells = <0>; 56651c580c6SStefan Roese compatible = "snps,dw-apb-gpio"; 56751c580c6SStefan Roese reg = <0xff709000 0x1000>; 56851c580c6SStefan Roese clocks = <&per_base_clk>; 56951c580c6SStefan Roese status = "disabled"; 57051c580c6SStefan Roese 57151c580c6SStefan Roese portb: gpio-controller@0 { 57251c580c6SStefan Roese compatible = "snps,dw-apb-gpio-port"; 573*660f53bcSMarek Vasut bank-name = "portb"; 57451c580c6SStefan Roese gpio-controller; 57551c580c6SStefan Roese #gpio-cells = <2>; 57651c580c6SStefan Roese snps,nr-gpios = <29>; 57751c580c6SStefan Roese reg = <0>; 57851c580c6SStefan Roese interrupt-controller; 57951c580c6SStefan Roese #interrupt-cells = <2>; 58051c580c6SStefan Roese interrupts = <0 165 4>; 58151c580c6SStefan Roese }; 58251c580c6SStefan Roese }; 58351c580c6SStefan Roese 58451c580c6SStefan Roese gpio2: gpio@ff70a000 { 58551c580c6SStefan Roese #address-cells = <1>; 58651c580c6SStefan Roese #size-cells = <0>; 58751c580c6SStefan Roese compatible = "snps,dw-apb-gpio"; 58851c580c6SStefan Roese reg = <0xff70a000 0x1000>; 58951c580c6SStefan Roese clocks = <&per_base_clk>; 59051c580c6SStefan Roese status = "disabled"; 59151c580c6SStefan Roese 59251c580c6SStefan Roese portc: gpio-controller@0 { 59351c580c6SStefan Roese compatible = "snps,dw-apb-gpio-port"; 594*660f53bcSMarek Vasut bank-name = "portc"; 59551c580c6SStefan Roese gpio-controller; 59651c580c6SStefan Roese #gpio-cells = <2>; 59751c580c6SStefan Roese snps,nr-gpios = <27>; 59851c580c6SStefan Roese reg = <0>; 59951c580c6SStefan Roese interrupt-controller; 60051c580c6SStefan Roese #interrupt-cells = <2>; 60151c580c6SStefan Roese interrupts = <0 166 4>; 60251c580c6SStefan Roese }; 60351c580c6SStefan Roese }; 60451c580c6SStefan Roese 60551c580c6SStefan Roese sdr: sdr@ffc25000 { 60651c580c6SStefan Roese compatible = "syscon"; 60751c580c6SStefan Roese reg = <0xffc25000 0x1000>; 60851c580c6SStefan Roese }; 60951c580c6SStefan Roese 61051c580c6SStefan Roese sdramedac { 61151c580c6SStefan Roese compatible = "altr,sdram-edac"; 61251c580c6SStefan Roese altr,sdr-syscon = <&sdr>; 61351c580c6SStefan Roese interrupts = <0 39 4>; 61451c580c6SStefan Roese }; 61551c580c6SStefan Roese 61651c580c6SStefan Roese L2: l2-cache@fffef000 { 61751c580c6SStefan Roese compatible = "arm,pl310-cache"; 61851c580c6SStefan Roese reg = <0xfffef000 0x1000>; 61951c580c6SStefan Roese interrupts = <0 38 0x04>; 62051c580c6SStefan Roese cache-unified; 62151c580c6SStefan Roese cache-level = <2>; 62251c580c6SStefan Roese arm,tag-latency = <1 1 1>; 62351c580c6SStefan Roese arm,data-latency = <2 1 1>; 62451c580c6SStefan Roese }; 62551c580c6SStefan Roese 626afe13993SMarek Vasut mmc0: dwmmc0@ff704000 { 62751c580c6SStefan Roese compatible = "altr,socfpga-dw-mshc"; 62851c580c6SStefan Roese reg = <0xff704000 0x1000>; 62951c580c6SStefan Roese interrupts = <0 139 4>; 63051c580c6SStefan Roese fifo-depth = <0x400>; 63151c580c6SStefan Roese #address-cells = <1>; 63251c580c6SStefan Roese #size-cells = <0>; 63351c580c6SStefan Roese clocks = <&l4_mp_clk>, <&sdmmc_clk>; 63451c580c6SStefan Roese clock-names = "biu", "ciu"; 63551c580c6SStefan Roese }; 63651c580c6SStefan Roese 637881f6a44SStefan Roese qspi: spi@ff705000 { 638881f6a44SStefan Roese compatible = "cadence,qspi"; 639881f6a44SStefan Roese #address-cells = <1>; 640881f6a44SStefan Roese #size-cells = <0>; 641881f6a44SStefan Roese reg = <0xff705000 0x1000>, 642881f6a44SStefan Roese <0xffa00000 0x1000>; 643881f6a44SStefan Roese interrupts = <0 151 4>; 644881f6a44SStefan Roese clocks = <&qspi_clk>; 645881f6a44SStefan Roese ext-decoder = <0>; /* external decoder */ 646653cda8fSMarek Vasut num-cs = <4>; 647881f6a44SStefan Roese fifo-depth = <128>; 64890a2f717SVikas Manocha sram-size = <128>; 649881f6a44SStefan Roese bus-num = <2>; 650881f6a44SStefan Roese status = "disabled"; 651881f6a44SStefan Roese }; 652881f6a44SStefan Roese 653ae79e2d2SStefan Roese spi0: spi@fff00000 { 65474114862SMarek Vasut compatible = "snps,dw-apb-ssi"; 655ae79e2d2SStefan Roese #address-cells = <1>; 656ae79e2d2SStefan Roese #size-cells = <0>; 657ae79e2d2SStefan Roese reg = <0xfff00000 0x1000>; 658ae79e2d2SStefan Roese interrupts = <0 154 4>; 659653cda8fSMarek Vasut num-cs = <4>; 660ae79e2d2SStefan Roese bus-num = <0>; 661ae79e2d2SStefan Roese tx-dma-channel = <&pdma 16>; 662ae79e2d2SStefan Roese rx-dma-channel = <&pdma 17>; 663ae79e2d2SStefan Roese clocks = <&per_base_clk>; 664ae79e2d2SStefan Roese status = "disabled"; 665ae79e2d2SStefan Roese }; 666ae79e2d2SStefan Roese 667ae79e2d2SStefan Roese spi1: spi@fff01000 { 66874114862SMarek Vasut compatible = "snps,dw-apb-ssi"; 669ae79e2d2SStefan Roese #address-cells = <1>; 670ae79e2d2SStefan Roese #size-cells = <0>; 671ae79e2d2SStefan Roese reg = <0xfff01000 0x1000>; 672ae79e2d2SStefan Roese interrupts = <0 156 4>; 673653cda8fSMarek Vasut num-cs = <4>; 674ae79e2d2SStefan Roese bus-num = <1>; 675ae79e2d2SStefan Roese tx-dma-channel = <&pdma 20>; 676ae79e2d2SStefan Roese rx-dma-channel = <&pdma 21>; 677ae79e2d2SStefan Roese clocks = <&per_base_clk>; 678ae79e2d2SStefan Roese status = "disabled"; 679ae79e2d2SStefan Roese }; 680ae79e2d2SStefan Roese 68151c580c6SStefan Roese /* Local timer */ 68251c580c6SStefan Roese timer@fffec600 { 68351c580c6SStefan Roese compatible = "arm,cortex-a9-twd-timer"; 68451c580c6SStefan Roese reg = <0xfffec600 0x100>; 68551c580c6SStefan Roese interrupts = <1 13 0xf04>; 68651c580c6SStefan Roese clocks = <&mpu_periph_clk>; 68751c580c6SStefan Roese }; 68851c580c6SStefan Roese 68951c580c6SStefan Roese timer0: timer0@ffc08000 { 69051c580c6SStefan Roese compatible = "snps,dw-apb-timer"; 69151c580c6SStefan Roese interrupts = <0 167 4>; 69251c580c6SStefan Roese reg = <0xffc08000 0x1000>; 69351c580c6SStefan Roese clocks = <&l4_sp_clk>; 69451c580c6SStefan Roese clock-names = "timer"; 69551c580c6SStefan Roese }; 69651c580c6SStefan Roese 69751c580c6SStefan Roese timer1: timer1@ffc09000 { 69851c580c6SStefan Roese compatible = "snps,dw-apb-timer"; 69951c580c6SStefan Roese interrupts = <0 168 4>; 70051c580c6SStefan Roese reg = <0xffc09000 0x1000>; 70151c580c6SStefan Roese clocks = <&l4_sp_clk>; 70251c580c6SStefan Roese clock-names = "timer"; 70351c580c6SStefan Roese }; 70451c580c6SStefan Roese 70551c580c6SStefan Roese timer2: timer2@ffd00000 { 70651c580c6SStefan Roese compatible = "snps,dw-apb-timer"; 70751c580c6SStefan Roese interrupts = <0 169 4>; 70851c580c6SStefan Roese reg = <0xffd00000 0x1000>; 70951c580c6SStefan Roese clocks = <&osc1>; 71051c580c6SStefan Roese clock-names = "timer"; 71151c580c6SStefan Roese }; 71251c580c6SStefan Roese 71351c580c6SStefan Roese timer3: timer3@ffd01000 { 71451c580c6SStefan Roese compatible = "snps,dw-apb-timer"; 71551c580c6SStefan Roese interrupts = <0 170 4>; 71651c580c6SStefan Roese reg = <0xffd01000 0x1000>; 71751c580c6SStefan Roese clocks = <&osc1>; 71851c580c6SStefan Roese clock-names = "timer"; 71951c580c6SStefan Roese }; 72051c580c6SStefan Roese 72151c580c6SStefan Roese uart0: serial0@ffc02000 { 72251c580c6SStefan Roese compatible = "snps,dw-apb-uart"; 72351c580c6SStefan Roese reg = <0xffc02000 0x1000>; 72451c580c6SStefan Roese interrupts = <0 162 4>; 72551c580c6SStefan Roese reg-shift = <2>; 72651c580c6SStefan Roese reg-io-width = <4>; 72751c580c6SStefan Roese clocks = <&l4_sp_clk>; 72851c580c6SStefan Roese }; 72951c580c6SStefan Roese 73051c580c6SStefan Roese uart1: serial1@ffc03000 { 73151c580c6SStefan Roese compatible = "snps,dw-apb-uart"; 73251c580c6SStefan Roese reg = <0xffc03000 0x1000>; 73351c580c6SStefan Roese interrupts = <0 163 4>; 73451c580c6SStefan Roese reg-shift = <2>; 73551c580c6SStefan Roese reg-io-width = <4>; 73651c580c6SStefan Roese clocks = <&l4_sp_clk>; 73751c580c6SStefan Roese }; 73851c580c6SStefan Roese 73951c580c6SStefan Roese rst: rstmgr@ffd05000 { 74051c580c6SStefan Roese #reset-cells = <1>; 74151c580c6SStefan Roese compatible = "altr,rst-mgr"; 74251c580c6SStefan Roese reg = <0xffd05000 0x1000>; 74351c580c6SStefan Roese }; 74451c580c6SStefan Roese 74551c580c6SStefan Roese usbphy0: usbphy@0 { 74651c580c6SStefan Roese #phy-cells = <0>; 74751c580c6SStefan Roese compatible = "usb-nop-xceiv"; 74851c580c6SStefan Roese status = "okay"; 74951c580c6SStefan Roese }; 75051c580c6SStefan Roese 75151c580c6SStefan Roese usb0: usb@ffb00000 { 75251c580c6SStefan Roese compatible = "snps,dwc2"; 75351c580c6SStefan Roese reg = <0xffb00000 0xffff>; 75451c580c6SStefan Roese interrupts = <0 125 4>; 75551c580c6SStefan Roese clocks = <&usb_mp_clk>; 75651c580c6SStefan Roese clock-names = "otg"; 75751c580c6SStefan Roese phys = <&usbphy0>; 75851c580c6SStefan Roese phy-names = "usb2-phy"; 75951c580c6SStefan Roese status = "disabled"; 76051c580c6SStefan Roese }; 76151c580c6SStefan Roese 76251c580c6SStefan Roese usb1: usb@ffb40000 { 76351c580c6SStefan Roese compatible = "snps,dwc2"; 76451c580c6SStefan Roese reg = <0xffb40000 0xffff>; 76551c580c6SStefan Roese interrupts = <0 128 4>; 76651c580c6SStefan Roese clocks = <&usb_mp_clk>; 76751c580c6SStefan Roese clock-names = "otg"; 76851c580c6SStefan Roese phys = <&usbphy0>; 76951c580c6SStefan Roese phy-names = "usb2-phy"; 77051c580c6SStefan Roese status = "disabled"; 77151c580c6SStefan Roese }; 77251c580c6SStefan Roese 77351c580c6SStefan Roese watchdog0: watchdog@ffd02000 { 77451c580c6SStefan Roese compatible = "snps,dw-wdt"; 77551c580c6SStefan Roese reg = <0xffd02000 0x1000>; 77651c580c6SStefan Roese interrupts = <0 171 4>; 77751c580c6SStefan Roese clocks = <&osc1>; 77851c580c6SStefan Roese status = "disabled"; 77951c580c6SStefan Roese }; 78051c580c6SStefan Roese 78151c580c6SStefan Roese watchdog1: watchdog@ffd03000 { 78251c580c6SStefan Roese compatible = "snps,dw-wdt"; 78351c580c6SStefan Roese reg = <0xffd03000 0x1000>; 78451c580c6SStefan Roese interrupts = <0 172 4>; 78551c580c6SStefan Roese clocks = <&osc1>; 78651c580c6SStefan Roese status = "disabled"; 78751c580c6SStefan Roese }; 78851c580c6SStefan Roese 78951c580c6SStefan Roese sysmgr: sysmgr@ffd08000 { 79051c580c6SStefan Roese compatible = "altr,sys-mgr", "syscon"; 79151c580c6SStefan Roese reg = <0xffd08000 0x4000>; 79251c580c6SStefan Roese }; 79351c580c6SStefan Roese }; 79451c580c6SStefan Roese}; 795