1*48038c4aSMugunthan V N/* 2*48038c4aSMugunthan V N * Device Tree Source for AM43xx clock data 3*48038c4aSMugunthan V N * 4*48038c4aSMugunthan V N * Copyright (C) 2013 Texas Instruments, Inc. 5*48038c4aSMugunthan V N * 6*48038c4aSMugunthan V N * This program is free software; you can redistribute it and/or modify 7*48038c4aSMugunthan V N * it under the terms of the GNU General Public License version 2 as 8*48038c4aSMugunthan V N * published by the Free Software Foundation. 9*48038c4aSMugunthan V N */ 10*48038c4aSMugunthan V N&scm_clocks { 11*48038c4aSMugunthan V N sys_clkin_ck: sys_clkin_ck { 12*48038c4aSMugunthan V N #clock-cells = <0>; 13*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 14*48038c4aSMugunthan V N clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; 15*48038c4aSMugunthan V N ti,bit-shift = <31>; 16*48038c4aSMugunthan V N reg = <0x0040>; 17*48038c4aSMugunthan V N }; 18*48038c4aSMugunthan V N 19*48038c4aSMugunthan V N crystal_freq_sel_ck: crystal_freq_sel_ck { 20*48038c4aSMugunthan V N #clock-cells = <0>; 21*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 22*48038c4aSMugunthan V N clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; 23*48038c4aSMugunthan V N ti,bit-shift = <29>; 24*48038c4aSMugunthan V N reg = <0x0040>; 25*48038c4aSMugunthan V N }; 26*48038c4aSMugunthan V N 27*48038c4aSMugunthan V N sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { 28*48038c4aSMugunthan V N #clock-cells = <0>; 29*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 30*48038c4aSMugunthan V N clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; 31*48038c4aSMugunthan V N ti,bit-shift = <22>; 32*48038c4aSMugunthan V N reg = <0x0040>; 33*48038c4aSMugunthan V N }; 34*48038c4aSMugunthan V N 35*48038c4aSMugunthan V N adc_tsc_fck: adc_tsc_fck { 36*48038c4aSMugunthan V N #clock-cells = <0>; 37*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 38*48038c4aSMugunthan V N clocks = <&sys_clkin_ck>; 39*48038c4aSMugunthan V N clock-mult = <1>; 40*48038c4aSMugunthan V N clock-div = <1>; 41*48038c4aSMugunthan V N }; 42*48038c4aSMugunthan V N 43*48038c4aSMugunthan V N dcan0_fck: dcan0_fck { 44*48038c4aSMugunthan V N #clock-cells = <0>; 45*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 46*48038c4aSMugunthan V N clocks = <&sys_clkin_ck>; 47*48038c4aSMugunthan V N clock-mult = <1>; 48*48038c4aSMugunthan V N clock-div = <1>; 49*48038c4aSMugunthan V N }; 50*48038c4aSMugunthan V N 51*48038c4aSMugunthan V N dcan1_fck: dcan1_fck { 52*48038c4aSMugunthan V N #clock-cells = <0>; 53*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 54*48038c4aSMugunthan V N clocks = <&sys_clkin_ck>; 55*48038c4aSMugunthan V N clock-mult = <1>; 56*48038c4aSMugunthan V N clock-div = <1>; 57*48038c4aSMugunthan V N }; 58*48038c4aSMugunthan V N 59*48038c4aSMugunthan V N mcasp0_fck: mcasp0_fck { 60*48038c4aSMugunthan V N #clock-cells = <0>; 61*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 62*48038c4aSMugunthan V N clocks = <&sys_clkin_ck>; 63*48038c4aSMugunthan V N clock-mult = <1>; 64*48038c4aSMugunthan V N clock-div = <1>; 65*48038c4aSMugunthan V N }; 66*48038c4aSMugunthan V N 67*48038c4aSMugunthan V N mcasp1_fck: mcasp1_fck { 68*48038c4aSMugunthan V N #clock-cells = <0>; 69*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 70*48038c4aSMugunthan V N clocks = <&sys_clkin_ck>; 71*48038c4aSMugunthan V N clock-mult = <1>; 72*48038c4aSMugunthan V N clock-div = <1>; 73*48038c4aSMugunthan V N }; 74*48038c4aSMugunthan V N 75*48038c4aSMugunthan V N smartreflex0_fck: smartreflex0_fck { 76*48038c4aSMugunthan V N #clock-cells = <0>; 77*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 78*48038c4aSMugunthan V N clocks = <&sys_clkin_ck>; 79*48038c4aSMugunthan V N clock-mult = <1>; 80*48038c4aSMugunthan V N clock-div = <1>; 81*48038c4aSMugunthan V N }; 82*48038c4aSMugunthan V N 83*48038c4aSMugunthan V N smartreflex1_fck: smartreflex1_fck { 84*48038c4aSMugunthan V N #clock-cells = <0>; 85*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 86*48038c4aSMugunthan V N clocks = <&sys_clkin_ck>; 87*48038c4aSMugunthan V N clock-mult = <1>; 88*48038c4aSMugunthan V N clock-div = <1>; 89*48038c4aSMugunthan V N }; 90*48038c4aSMugunthan V N 91*48038c4aSMugunthan V N sha0_fck: sha0_fck { 92*48038c4aSMugunthan V N #clock-cells = <0>; 93*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 94*48038c4aSMugunthan V N clocks = <&sys_clkin_ck>; 95*48038c4aSMugunthan V N clock-mult = <1>; 96*48038c4aSMugunthan V N clock-div = <1>; 97*48038c4aSMugunthan V N }; 98*48038c4aSMugunthan V N 99*48038c4aSMugunthan V N aes0_fck: aes0_fck { 100*48038c4aSMugunthan V N #clock-cells = <0>; 101*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 102*48038c4aSMugunthan V N clocks = <&sys_clkin_ck>; 103*48038c4aSMugunthan V N clock-mult = <1>; 104*48038c4aSMugunthan V N clock-div = <1>; 105*48038c4aSMugunthan V N }; 106*48038c4aSMugunthan V N 107*48038c4aSMugunthan V N ehrpwm0_tbclk: ehrpwm0_tbclk { 108*48038c4aSMugunthan V N #clock-cells = <0>; 109*48038c4aSMugunthan V N compatible = "ti,gate-clock"; 110*48038c4aSMugunthan V N clocks = <&l4ls_gclk>; 111*48038c4aSMugunthan V N ti,bit-shift = <0>; 112*48038c4aSMugunthan V N reg = <0x0664>; 113*48038c4aSMugunthan V N }; 114*48038c4aSMugunthan V N 115*48038c4aSMugunthan V N ehrpwm1_tbclk: ehrpwm1_tbclk { 116*48038c4aSMugunthan V N #clock-cells = <0>; 117*48038c4aSMugunthan V N compatible = "ti,gate-clock"; 118*48038c4aSMugunthan V N clocks = <&l4ls_gclk>; 119*48038c4aSMugunthan V N ti,bit-shift = <1>; 120*48038c4aSMugunthan V N reg = <0x0664>; 121*48038c4aSMugunthan V N }; 122*48038c4aSMugunthan V N 123*48038c4aSMugunthan V N ehrpwm2_tbclk: ehrpwm2_tbclk { 124*48038c4aSMugunthan V N #clock-cells = <0>; 125*48038c4aSMugunthan V N compatible = "ti,gate-clock"; 126*48038c4aSMugunthan V N clocks = <&l4ls_gclk>; 127*48038c4aSMugunthan V N ti,bit-shift = <2>; 128*48038c4aSMugunthan V N reg = <0x0664>; 129*48038c4aSMugunthan V N }; 130*48038c4aSMugunthan V N 131*48038c4aSMugunthan V N ehrpwm3_tbclk: ehrpwm3_tbclk { 132*48038c4aSMugunthan V N #clock-cells = <0>; 133*48038c4aSMugunthan V N compatible = "ti,gate-clock"; 134*48038c4aSMugunthan V N clocks = <&l4ls_gclk>; 135*48038c4aSMugunthan V N ti,bit-shift = <4>; 136*48038c4aSMugunthan V N reg = <0x0664>; 137*48038c4aSMugunthan V N }; 138*48038c4aSMugunthan V N 139*48038c4aSMugunthan V N ehrpwm4_tbclk: ehrpwm4_tbclk { 140*48038c4aSMugunthan V N #clock-cells = <0>; 141*48038c4aSMugunthan V N compatible = "ti,gate-clock"; 142*48038c4aSMugunthan V N clocks = <&l4ls_gclk>; 143*48038c4aSMugunthan V N ti,bit-shift = <5>; 144*48038c4aSMugunthan V N reg = <0x0664>; 145*48038c4aSMugunthan V N }; 146*48038c4aSMugunthan V N 147*48038c4aSMugunthan V N ehrpwm5_tbclk: ehrpwm5_tbclk { 148*48038c4aSMugunthan V N #clock-cells = <0>; 149*48038c4aSMugunthan V N compatible = "ti,gate-clock"; 150*48038c4aSMugunthan V N clocks = <&l4ls_gclk>; 151*48038c4aSMugunthan V N ti,bit-shift = <6>; 152*48038c4aSMugunthan V N reg = <0x0664>; 153*48038c4aSMugunthan V N }; 154*48038c4aSMugunthan V N}; 155*48038c4aSMugunthan V N&prcm_clocks { 156*48038c4aSMugunthan V N clk_32768_ck: clk_32768_ck { 157*48038c4aSMugunthan V N #clock-cells = <0>; 158*48038c4aSMugunthan V N compatible = "fixed-clock"; 159*48038c4aSMugunthan V N clock-frequency = <32768>; 160*48038c4aSMugunthan V N }; 161*48038c4aSMugunthan V N 162*48038c4aSMugunthan V N clk_rc32k_ck: clk_rc32k_ck { 163*48038c4aSMugunthan V N #clock-cells = <0>; 164*48038c4aSMugunthan V N compatible = "fixed-clock"; 165*48038c4aSMugunthan V N clock-frequency = <32768>; 166*48038c4aSMugunthan V N }; 167*48038c4aSMugunthan V N 168*48038c4aSMugunthan V N virt_19200000_ck: virt_19200000_ck { 169*48038c4aSMugunthan V N #clock-cells = <0>; 170*48038c4aSMugunthan V N compatible = "fixed-clock"; 171*48038c4aSMugunthan V N clock-frequency = <19200000>; 172*48038c4aSMugunthan V N }; 173*48038c4aSMugunthan V N 174*48038c4aSMugunthan V N virt_24000000_ck: virt_24000000_ck { 175*48038c4aSMugunthan V N #clock-cells = <0>; 176*48038c4aSMugunthan V N compatible = "fixed-clock"; 177*48038c4aSMugunthan V N clock-frequency = <24000000>; 178*48038c4aSMugunthan V N }; 179*48038c4aSMugunthan V N 180*48038c4aSMugunthan V N virt_25000000_ck: virt_25000000_ck { 181*48038c4aSMugunthan V N #clock-cells = <0>; 182*48038c4aSMugunthan V N compatible = "fixed-clock"; 183*48038c4aSMugunthan V N clock-frequency = <25000000>; 184*48038c4aSMugunthan V N }; 185*48038c4aSMugunthan V N 186*48038c4aSMugunthan V N virt_26000000_ck: virt_26000000_ck { 187*48038c4aSMugunthan V N #clock-cells = <0>; 188*48038c4aSMugunthan V N compatible = "fixed-clock"; 189*48038c4aSMugunthan V N clock-frequency = <26000000>; 190*48038c4aSMugunthan V N }; 191*48038c4aSMugunthan V N 192*48038c4aSMugunthan V N tclkin_ck: tclkin_ck { 193*48038c4aSMugunthan V N #clock-cells = <0>; 194*48038c4aSMugunthan V N compatible = "fixed-clock"; 195*48038c4aSMugunthan V N clock-frequency = <26000000>; 196*48038c4aSMugunthan V N }; 197*48038c4aSMugunthan V N 198*48038c4aSMugunthan V N dpll_core_ck: dpll_core_ck { 199*48038c4aSMugunthan V N #clock-cells = <0>; 200*48038c4aSMugunthan V N compatible = "ti,am3-dpll-core-clock"; 201*48038c4aSMugunthan V N clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 202*48038c4aSMugunthan V N reg = <0x2d20>, <0x2d24>, <0x2d2c>; 203*48038c4aSMugunthan V N }; 204*48038c4aSMugunthan V N 205*48038c4aSMugunthan V N dpll_core_x2_ck: dpll_core_x2_ck { 206*48038c4aSMugunthan V N #clock-cells = <0>; 207*48038c4aSMugunthan V N compatible = "ti,am3-dpll-x2-clock"; 208*48038c4aSMugunthan V N clocks = <&dpll_core_ck>; 209*48038c4aSMugunthan V N }; 210*48038c4aSMugunthan V N 211*48038c4aSMugunthan V N dpll_core_m4_ck: dpll_core_m4_ck { 212*48038c4aSMugunthan V N #clock-cells = <0>; 213*48038c4aSMugunthan V N compatible = "ti,divider-clock"; 214*48038c4aSMugunthan V N clocks = <&dpll_core_x2_ck>; 215*48038c4aSMugunthan V N ti,max-div = <31>; 216*48038c4aSMugunthan V N ti,autoidle-shift = <8>; 217*48038c4aSMugunthan V N reg = <0x2d38>; 218*48038c4aSMugunthan V N ti,index-starts-at-one; 219*48038c4aSMugunthan V N ti,invert-autoidle-bit; 220*48038c4aSMugunthan V N }; 221*48038c4aSMugunthan V N 222*48038c4aSMugunthan V N dpll_core_m5_ck: dpll_core_m5_ck { 223*48038c4aSMugunthan V N #clock-cells = <0>; 224*48038c4aSMugunthan V N compatible = "ti,divider-clock"; 225*48038c4aSMugunthan V N clocks = <&dpll_core_x2_ck>; 226*48038c4aSMugunthan V N ti,max-div = <31>; 227*48038c4aSMugunthan V N ti,autoidle-shift = <8>; 228*48038c4aSMugunthan V N reg = <0x2d3c>; 229*48038c4aSMugunthan V N ti,index-starts-at-one; 230*48038c4aSMugunthan V N ti,invert-autoidle-bit; 231*48038c4aSMugunthan V N }; 232*48038c4aSMugunthan V N 233*48038c4aSMugunthan V N dpll_core_m6_ck: dpll_core_m6_ck { 234*48038c4aSMugunthan V N #clock-cells = <0>; 235*48038c4aSMugunthan V N compatible = "ti,divider-clock"; 236*48038c4aSMugunthan V N clocks = <&dpll_core_x2_ck>; 237*48038c4aSMugunthan V N ti,max-div = <31>; 238*48038c4aSMugunthan V N ti,autoidle-shift = <8>; 239*48038c4aSMugunthan V N reg = <0x2d40>; 240*48038c4aSMugunthan V N ti,index-starts-at-one; 241*48038c4aSMugunthan V N ti,invert-autoidle-bit; 242*48038c4aSMugunthan V N }; 243*48038c4aSMugunthan V N 244*48038c4aSMugunthan V N dpll_mpu_ck: dpll_mpu_ck { 245*48038c4aSMugunthan V N #clock-cells = <0>; 246*48038c4aSMugunthan V N compatible = "ti,am3-dpll-clock"; 247*48038c4aSMugunthan V N clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 248*48038c4aSMugunthan V N reg = <0x2d60>, <0x2d64>, <0x2d6c>; 249*48038c4aSMugunthan V N }; 250*48038c4aSMugunthan V N 251*48038c4aSMugunthan V N dpll_mpu_m2_ck: dpll_mpu_m2_ck { 252*48038c4aSMugunthan V N #clock-cells = <0>; 253*48038c4aSMugunthan V N compatible = "ti,divider-clock"; 254*48038c4aSMugunthan V N clocks = <&dpll_mpu_ck>; 255*48038c4aSMugunthan V N ti,max-div = <31>; 256*48038c4aSMugunthan V N ti,autoidle-shift = <8>; 257*48038c4aSMugunthan V N reg = <0x2d70>; 258*48038c4aSMugunthan V N ti,index-starts-at-one; 259*48038c4aSMugunthan V N ti,invert-autoidle-bit; 260*48038c4aSMugunthan V N }; 261*48038c4aSMugunthan V N 262*48038c4aSMugunthan V N dpll_ddr_ck: dpll_ddr_ck { 263*48038c4aSMugunthan V N #clock-cells = <0>; 264*48038c4aSMugunthan V N compatible = "ti,am3-dpll-clock"; 265*48038c4aSMugunthan V N clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 266*48038c4aSMugunthan V N reg = <0x2da0>, <0x2da4>, <0x2dac>; 267*48038c4aSMugunthan V N }; 268*48038c4aSMugunthan V N 269*48038c4aSMugunthan V N dpll_ddr_m2_ck: dpll_ddr_m2_ck { 270*48038c4aSMugunthan V N #clock-cells = <0>; 271*48038c4aSMugunthan V N compatible = "ti,divider-clock"; 272*48038c4aSMugunthan V N clocks = <&dpll_ddr_ck>; 273*48038c4aSMugunthan V N ti,max-div = <31>; 274*48038c4aSMugunthan V N ti,autoidle-shift = <8>; 275*48038c4aSMugunthan V N reg = <0x2db0>; 276*48038c4aSMugunthan V N ti,index-starts-at-one; 277*48038c4aSMugunthan V N ti,invert-autoidle-bit; 278*48038c4aSMugunthan V N }; 279*48038c4aSMugunthan V N 280*48038c4aSMugunthan V N dpll_disp_ck: dpll_disp_ck { 281*48038c4aSMugunthan V N #clock-cells = <0>; 282*48038c4aSMugunthan V N compatible = "ti,am3-dpll-clock"; 283*48038c4aSMugunthan V N clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 284*48038c4aSMugunthan V N reg = <0x2e20>, <0x2e24>, <0x2e2c>; 285*48038c4aSMugunthan V N }; 286*48038c4aSMugunthan V N 287*48038c4aSMugunthan V N dpll_disp_m2_ck: dpll_disp_m2_ck { 288*48038c4aSMugunthan V N #clock-cells = <0>; 289*48038c4aSMugunthan V N compatible = "ti,divider-clock"; 290*48038c4aSMugunthan V N clocks = <&dpll_disp_ck>; 291*48038c4aSMugunthan V N ti,max-div = <31>; 292*48038c4aSMugunthan V N ti,autoidle-shift = <8>; 293*48038c4aSMugunthan V N reg = <0x2e30>; 294*48038c4aSMugunthan V N ti,index-starts-at-one; 295*48038c4aSMugunthan V N ti,invert-autoidle-bit; 296*48038c4aSMugunthan V N ti,set-rate-parent; 297*48038c4aSMugunthan V N }; 298*48038c4aSMugunthan V N 299*48038c4aSMugunthan V N dpll_per_ck: dpll_per_ck { 300*48038c4aSMugunthan V N #clock-cells = <0>; 301*48038c4aSMugunthan V N compatible = "ti,am3-dpll-j-type-clock"; 302*48038c4aSMugunthan V N clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 303*48038c4aSMugunthan V N reg = <0x2de0>, <0x2de4>, <0x2dec>; 304*48038c4aSMugunthan V N }; 305*48038c4aSMugunthan V N 306*48038c4aSMugunthan V N dpll_per_m2_ck: dpll_per_m2_ck { 307*48038c4aSMugunthan V N #clock-cells = <0>; 308*48038c4aSMugunthan V N compatible = "ti,divider-clock"; 309*48038c4aSMugunthan V N clocks = <&dpll_per_ck>; 310*48038c4aSMugunthan V N ti,max-div = <127>; 311*48038c4aSMugunthan V N ti,autoidle-shift = <8>; 312*48038c4aSMugunthan V N reg = <0x2df0>; 313*48038c4aSMugunthan V N ti,index-starts-at-one; 314*48038c4aSMugunthan V N ti,invert-autoidle-bit; 315*48038c4aSMugunthan V N }; 316*48038c4aSMugunthan V N 317*48038c4aSMugunthan V N dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { 318*48038c4aSMugunthan V N #clock-cells = <0>; 319*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 320*48038c4aSMugunthan V N clocks = <&dpll_per_m2_ck>; 321*48038c4aSMugunthan V N clock-mult = <1>; 322*48038c4aSMugunthan V N clock-div = <4>; 323*48038c4aSMugunthan V N }; 324*48038c4aSMugunthan V N 325*48038c4aSMugunthan V N dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { 326*48038c4aSMugunthan V N #clock-cells = <0>; 327*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 328*48038c4aSMugunthan V N clocks = <&dpll_per_m2_ck>; 329*48038c4aSMugunthan V N clock-mult = <1>; 330*48038c4aSMugunthan V N clock-div = <4>; 331*48038c4aSMugunthan V N }; 332*48038c4aSMugunthan V N 333*48038c4aSMugunthan V N clk_24mhz: clk_24mhz { 334*48038c4aSMugunthan V N #clock-cells = <0>; 335*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 336*48038c4aSMugunthan V N clocks = <&dpll_per_m2_ck>; 337*48038c4aSMugunthan V N clock-mult = <1>; 338*48038c4aSMugunthan V N clock-div = <8>; 339*48038c4aSMugunthan V N }; 340*48038c4aSMugunthan V N 341*48038c4aSMugunthan V N clkdiv32k_ck: clkdiv32k_ck { 342*48038c4aSMugunthan V N #clock-cells = <0>; 343*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 344*48038c4aSMugunthan V N clocks = <&clk_24mhz>; 345*48038c4aSMugunthan V N clock-mult = <1>; 346*48038c4aSMugunthan V N clock-div = <732>; 347*48038c4aSMugunthan V N }; 348*48038c4aSMugunthan V N 349*48038c4aSMugunthan V N clkdiv32k_ick: clkdiv32k_ick { 350*48038c4aSMugunthan V N #clock-cells = <0>; 351*48038c4aSMugunthan V N compatible = "ti,gate-clock"; 352*48038c4aSMugunthan V N clocks = <&clkdiv32k_ck>; 353*48038c4aSMugunthan V N ti,bit-shift = <8>; 354*48038c4aSMugunthan V N reg = <0x2a38>; 355*48038c4aSMugunthan V N }; 356*48038c4aSMugunthan V N 357*48038c4aSMugunthan V N sysclk_div: sysclk_div { 358*48038c4aSMugunthan V N #clock-cells = <0>; 359*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 360*48038c4aSMugunthan V N clocks = <&dpll_core_m4_ck>; 361*48038c4aSMugunthan V N clock-mult = <1>; 362*48038c4aSMugunthan V N clock-div = <1>; 363*48038c4aSMugunthan V N }; 364*48038c4aSMugunthan V N 365*48038c4aSMugunthan V N pruss_ocp_gclk: pruss_ocp_gclk { 366*48038c4aSMugunthan V N #clock-cells = <0>; 367*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 368*48038c4aSMugunthan V N clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; 369*48038c4aSMugunthan V N reg = <0x4248>; 370*48038c4aSMugunthan V N }; 371*48038c4aSMugunthan V N 372*48038c4aSMugunthan V N clk_32k_tpm_ck: clk_32k_tpm_ck { 373*48038c4aSMugunthan V N #clock-cells = <0>; 374*48038c4aSMugunthan V N compatible = "fixed-clock"; 375*48038c4aSMugunthan V N clock-frequency = <32768>; 376*48038c4aSMugunthan V N }; 377*48038c4aSMugunthan V N 378*48038c4aSMugunthan V N timer1_fck: timer1_fck { 379*48038c4aSMugunthan V N #clock-cells = <0>; 380*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 381*48038c4aSMugunthan V N clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; 382*48038c4aSMugunthan V N reg = <0x4200>; 383*48038c4aSMugunthan V N }; 384*48038c4aSMugunthan V N 385*48038c4aSMugunthan V N timer2_fck: timer2_fck { 386*48038c4aSMugunthan V N #clock-cells = <0>; 387*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 388*48038c4aSMugunthan V N clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 389*48038c4aSMugunthan V N reg = <0x4204>; 390*48038c4aSMugunthan V N }; 391*48038c4aSMugunthan V N 392*48038c4aSMugunthan V N timer3_fck: timer3_fck { 393*48038c4aSMugunthan V N #clock-cells = <0>; 394*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 395*48038c4aSMugunthan V N clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 396*48038c4aSMugunthan V N reg = <0x4208>; 397*48038c4aSMugunthan V N }; 398*48038c4aSMugunthan V N 399*48038c4aSMugunthan V N timer4_fck: timer4_fck { 400*48038c4aSMugunthan V N #clock-cells = <0>; 401*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 402*48038c4aSMugunthan V N clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 403*48038c4aSMugunthan V N reg = <0x420c>; 404*48038c4aSMugunthan V N }; 405*48038c4aSMugunthan V N 406*48038c4aSMugunthan V N timer5_fck: timer5_fck { 407*48038c4aSMugunthan V N #clock-cells = <0>; 408*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 409*48038c4aSMugunthan V N clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 410*48038c4aSMugunthan V N reg = <0x4210>; 411*48038c4aSMugunthan V N }; 412*48038c4aSMugunthan V N 413*48038c4aSMugunthan V N timer6_fck: timer6_fck { 414*48038c4aSMugunthan V N #clock-cells = <0>; 415*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 416*48038c4aSMugunthan V N clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 417*48038c4aSMugunthan V N reg = <0x4214>; 418*48038c4aSMugunthan V N }; 419*48038c4aSMugunthan V N 420*48038c4aSMugunthan V N timer7_fck: timer7_fck { 421*48038c4aSMugunthan V N #clock-cells = <0>; 422*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 423*48038c4aSMugunthan V N clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 424*48038c4aSMugunthan V N reg = <0x4218>; 425*48038c4aSMugunthan V N }; 426*48038c4aSMugunthan V N 427*48038c4aSMugunthan V N wdt1_fck: wdt1_fck { 428*48038c4aSMugunthan V N #clock-cells = <0>; 429*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 430*48038c4aSMugunthan V N clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; 431*48038c4aSMugunthan V N reg = <0x422c>; 432*48038c4aSMugunthan V N }; 433*48038c4aSMugunthan V N 434*48038c4aSMugunthan V N l3_gclk: l3_gclk { 435*48038c4aSMugunthan V N #clock-cells = <0>; 436*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 437*48038c4aSMugunthan V N clocks = <&dpll_core_m4_ck>; 438*48038c4aSMugunthan V N clock-mult = <1>; 439*48038c4aSMugunthan V N clock-div = <1>; 440*48038c4aSMugunthan V N }; 441*48038c4aSMugunthan V N 442*48038c4aSMugunthan V N dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { 443*48038c4aSMugunthan V N #clock-cells = <0>; 444*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 445*48038c4aSMugunthan V N clocks = <&sysclk_div>; 446*48038c4aSMugunthan V N clock-mult = <1>; 447*48038c4aSMugunthan V N clock-div = <2>; 448*48038c4aSMugunthan V N }; 449*48038c4aSMugunthan V N 450*48038c4aSMugunthan V N l4hs_gclk: l4hs_gclk { 451*48038c4aSMugunthan V N #clock-cells = <0>; 452*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 453*48038c4aSMugunthan V N clocks = <&dpll_core_m4_ck>; 454*48038c4aSMugunthan V N clock-mult = <1>; 455*48038c4aSMugunthan V N clock-div = <1>; 456*48038c4aSMugunthan V N }; 457*48038c4aSMugunthan V N 458*48038c4aSMugunthan V N l3s_gclk: l3s_gclk { 459*48038c4aSMugunthan V N #clock-cells = <0>; 460*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 461*48038c4aSMugunthan V N clocks = <&dpll_core_m4_div2_ck>; 462*48038c4aSMugunthan V N clock-mult = <1>; 463*48038c4aSMugunthan V N clock-div = <1>; 464*48038c4aSMugunthan V N }; 465*48038c4aSMugunthan V N 466*48038c4aSMugunthan V N l4ls_gclk: l4ls_gclk { 467*48038c4aSMugunthan V N #clock-cells = <0>; 468*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 469*48038c4aSMugunthan V N clocks = <&dpll_core_m4_div2_ck>; 470*48038c4aSMugunthan V N clock-mult = <1>; 471*48038c4aSMugunthan V N clock-div = <1>; 472*48038c4aSMugunthan V N }; 473*48038c4aSMugunthan V N 474*48038c4aSMugunthan V N cpsw_125mhz_gclk: cpsw_125mhz_gclk { 475*48038c4aSMugunthan V N #clock-cells = <0>; 476*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 477*48038c4aSMugunthan V N clocks = <&dpll_core_m5_ck>; 478*48038c4aSMugunthan V N clock-mult = <1>; 479*48038c4aSMugunthan V N clock-div = <2>; 480*48038c4aSMugunthan V N }; 481*48038c4aSMugunthan V N 482*48038c4aSMugunthan V N cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { 483*48038c4aSMugunthan V N #clock-cells = <0>; 484*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 485*48038c4aSMugunthan V N clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; 486*48038c4aSMugunthan V N reg = <0x4238>; 487*48038c4aSMugunthan V N }; 488*48038c4aSMugunthan V N 489*48038c4aSMugunthan V N clk_32k_mosc_ck: clk_32k_mosc_ck { 490*48038c4aSMugunthan V N #clock-cells = <0>; 491*48038c4aSMugunthan V N compatible = "fixed-clock"; 492*48038c4aSMugunthan V N clock-frequency = <32768>; 493*48038c4aSMugunthan V N }; 494*48038c4aSMugunthan V N 495*48038c4aSMugunthan V N gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck { 496*48038c4aSMugunthan V N #clock-cells = <0>; 497*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 498*48038c4aSMugunthan V N clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; 499*48038c4aSMugunthan V N reg = <0x4240>; 500*48038c4aSMugunthan V N }; 501*48038c4aSMugunthan V N 502*48038c4aSMugunthan V N gpio0_dbclk: gpio0_dbclk { 503*48038c4aSMugunthan V N #clock-cells = <0>; 504*48038c4aSMugunthan V N compatible = "ti,gate-clock"; 505*48038c4aSMugunthan V N clocks = <&gpio0_dbclk_mux_ck>; 506*48038c4aSMugunthan V N ti,bit-shift = <8>; 507*48038c4aSMugunthan V N reg = <0x2b68>; 508*48038c4aSMugunthan V N }; 509*48038c4aSMugunthan V N 510*48038c4aSMugunthan V N gpio1_dbclk: gpio1_dbclk { 511*48038c4aSMugunthan V N #clock-cells = <0>; 512*48038c4aSMugunthan V N compatible = "ti,gate-clock"; 513*48038c4aSMugunthan V N clocks = <&clkdiv32k_ick>; 514*48038c4aSMugunthan V N ti,bit-shift = <8>; 515*48038c4aSMugunthan V N reg = <0x8c78>; 516*48038c4aSMugunthan V N }; 517*48038c4aSMugunthan V N 518*48038c4aSMugunthan V N gpio2_dbclk: gpio2_dbclk { 519*48038c4aSMugunthan V N #clock-cells = <0>; 520*48038c4aSMugunthan V N compatible = "ti,gate-clock"; 521*48038c4aSMugunthan V N clocks = <&clkdiv32k_ick>; 522*48038c4aSMugunthan V N ti,bit-shift = <8>; 523*48038c4aSMugunthan V N reg = <0x8c80>; 524*48038c4aSMugunthan V N }; 525*48038c4aSMugunthan V N 526*48038c4aSMugunthan V N gpio3_dbclk: gpio3_dbclk { 527*48038c4aSMugunthan V N #clock-cells = <0>; 528*48038c4aSMugunthan V N compatible = "ti,gate-clock"; 529*48038c4aSMugunthan V N clocks = <&clkdiv32k_ick>; 530*48038c4aSMugunthan V N ti,bit-shift = <8>; 531*48038c4aSMugunthan V N reg = <0x8c88>; 532*48038c4aSMugunthan V N }; 533*48038c4aSMugunthan V N 534*48038c4aSMugunthan V N gpio4_dbclk: gpio4_dbclk { 535*48038c4aSMugunthan V N #clock-cells = <0>; 536*48038c4aSMugunthan V N compatible = "ti,gate-clock"; 537*48038c4aSMugunthan V N clocks = <&clkdiv32k_ick>; 538*48038c4aSMugunthan V N ti,bit-shift = <8>; 539*48038c4aSMugunthan V N reg = <0x8c90>; 540*48038c4aSMugunthan V N }; 541*48038c4aSMugunthan V N 542*48038c4aSMugunthan V N gpio5_dbclk: gpio5_dbclk { 543*48038c4aSMugunthan V N #clock-cells = <0>; 544*48038c4aSMugunthan V N compatible = "ti,gate-clock"; 545*48038c4aSMugunthan V N clocks = <&clkdiv32k_ick>; 546*48038c4aSMugunthan V N ti,bit-shift = <8>; 547*48038c4aSMugunthan V N reg = <0x8c98>; 548*48038c4aSMugunthan V N }; 549*48038c4aSMugunthan V N 550*48038c4aSMugunthan V N mmc_clk: mmc_clk { 551*48038c4aSMugunthan V N #clock-cells = <0>; 552*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 553*48038c4aSMugunthan V N clocks = <&dpll_per_m2_ck>; 554*48038c4aSMugunthan V N clock-mult = <1>; 555*48038c4aSMugunthan V N clock-div = <2>; 556*48038c4aSMugunthan V N }; 557*48038c4aSMugunthan V N 558*48038c4aSMugunthan V N gfx_fclk_clksel_ck: gfx_fclk_clksel_ck { 559*48038c4aSMugunthan V N #clock-cells = <0>; 560*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 561*48038c4aSMugunthan V N clocks = <&sysclk_div>, <&dpll_per_m2_ck>; 562*48038c4aSMugunthan V N ti,bit-shift = <1>; 563*48038c4aSMugunthan V N reg = <0x423c>; 564*48038c4aSMugunthan V N }; 565*48038c4aSMugunthan V N 566*48038c4aSMugunthan V N gfx_fck_div_ck: gfx_fck_div_ck { 567*48038c4aSMugunthan V N #clock-cells = <0>; 568*48038c4aSMugunthan V N compatible = "ti,divider-clock"; 569*48038c4aSMugunthan V N clocks = <&gfx_fclk_clksel_ck>; 570*48038c4aSMugunthan V N reg = <0x423c>; 571*48038c4aSMugunthan V N ti,max-div = <2>; 572*48038c4aSMugunthan V N }; 573*48038c4aSMugunthan V N 574*48038c4aSMugunthan V N disp_clk: disp_clk { 575*48038c4aSMugunthan V N #clock-cells = <0>; 576*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 577*48038c4aSMugunthan V N clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; 578*48038c4aSMugunthan V N reg = <0x4244>; 579*48038c4aSMugunthan V N ti,set-rate-parent; 580*48038c4aSMugunthan V N }; 581*48038c4aSMugunthan V N 582*48038c4aSMugunthan V N dpll_extdev_ck: dpll_extdev_ck { 583*48038c4aSMugunthan V N #clock-cells = <0>; 584*48038c4aSMugunthan V N compatible = "ti,am3-dpll-clock"; 585*48038c4aSMugunthan V N clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 586*48038c4aSMugunthan V N reg = <0x2e60>, <0x2e64>, <0x2e6c>; 587*48038c4aSMugunthan V N }; 588*48038c4aSMugunthan V N 589*48038c4aSMugunthan V N dpll_extdev_m2_ck: dpll_extdev_m2_ck { 590*48038c4aSMugunthan V N #clock-cells = <0>; 591*48038c4aSMugunthan V N compatible = "ti,divider-clock"; 592*48038c4aSMugunthan V N clocks = <&dpll_extdev_ck>; 593*48038c4aSMugunthan V N ti,max-div = <127>; 594*48038c4aSMugunthan V N ti,autoidle-shift = <8>; 595*48038c4aSMugunthan V N reg = <0x2e70>; 596*48038c4aSMugunthan V N ti,index-starts-at-one; 597*48038c4aSMugunthan V N ti,invert-autoidle-bit; 598*48038c4aSMugunthan V N }; 599*48038c4aSMugunthan V N 600*48038c4aSMugunthan V N mux_synctimer32k_ck: mux_synctimer32k_ck { 601*48038c4aSMugunthan V N #clock-cells = <0>; 602*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 603*48038c4aSMugunthan V N clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; 604*48038c4aSMugunthan V N reg = <0x4230>; 605*48038c4aSMugunthan V N }; 606*48038c4aSMugunthan V N 607*48038c4aSMugunthan V N synctimer_32kclk: synctimer_32kclk { 608*48038c4aSMugunthan V N #clock-cells = <0>; 609*48038c4aSMugunthan V N compatible = "ti,gate-clock"; 610*48038c4aSMugunthan V N clocks = <&mux_synctimer32k_ck>; 611*48038c4aSMugunthan V N ti,bit-shift = <8>; 612*48038c4aSMugunthan V N reg = <0x2a30>; 613*48038c4aSMugunthan V N }; 614*48038c4aSMugunthan V N 615*48038c4aSMugunthan V N timer8_fck: timer8_fck { 616*48038c4aSMugunthan V N #clock-cells = <0>; 617*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 618*48038c4aSMugunthan V N clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 619*48038c4aSMugunthan V N reg = <0x421c>; 620*48038c4aSMugunthan V N }; 621*48038c4aSMugunthan V N 622*48038c4aSMugunthan V N timer9_fck: timer9_fck { 623*48038c4aSMugunthan V N #clock-cells = <0>; 624*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 625*48038c4aSMugunthan V N clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 626*48038c4aSMugunthan V N reg = <0x4220>; 627*48038c4aSMugunthan V N }; 628*48038c4aSMugunthan V N 629*48038c4aSMugunthan V N timer10_fck: timer10_fck { 630*48038c4aSMugunthan V N #clock-cells = <0>; 631*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 632*48038c4aSMugunthan V N clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 633*48038c4aSMugunthan V N reg = <0x4224>; 634*48038c4aSMugunthan V N }; 635*48038c4aSMugunthan V N 636*48038c4aSMugunthan V N timer11_fck: timer11_fck { 637*48038c4aSMugunthan V N #clock-cells = <0>; 638*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 639*48038c4aSMugunthan V N clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 640*48038c4aSMugunthan V N reg = <0x4228>; 641*48038c4aSMugunthan V N }; 642*48038c4aSMugunthan V N 643*48038c4aSMugunthan V N cpsw_50m_clkdiv: cpsw_50m_clkdiv { 644*48038c4aSMugunthan V N #clock-cells = <0>; 645*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 646*48038c4aSMugunthan V N clocks = <&dpll_core_m5_ck>; 647*48038c4aSMugunthan V N clock-mult = <1>; 648*48038c4aSMugunthan V N clock-div = <1>; 649*48038c4aSMugunthan V N }; 650*48038c4aSMugunthan V N 651*48038c4aSMugunthan V N cpsw_5m_clkdiv: cpsw_5m_clkdiv { 652*48038c4aSMugunthan V N #clock-cells = <0>; 653*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 654*48038c4aSMugunthan V N clocks = <&cpsw_50m_clkdiv>; 655*48038c4aSMugunthan V N clock-mult = <1>; 656*48038c4aSMugunthan V N clock-div = <10>; 657*48038c4aSMugunthan V N }; 658*48038c4aSMugunthan V N 659*48038c4aSMugunthan V N dpll_ddr_x2_ck: dpll_ddr_x2_ck { 660*48038c4aSMugunthan V N #clock-cells = <0>; 661*48038c4aSMugunthan V N compatible = "ti,am3-dpll-x2-clock"; 662*48038c4aSMugunthan V N clocks = <&dpll_ddr_ck>; 663*48038c4aSMugunthan V N }; 664*48038c4aSMugunthan V N 665*48038c4aSMugunthan V N dpll_ddr_m4_ck: dpll_ddr_m4_ck { 666*48038c4aSMugunthan V N #clock-cells = <0>; 667*48038c4aSMugunthan V N compatible = "ti,divider-clock"; 668*48038c4aSMugunthan V N clocks = <&dpll_ddr_x2_ck>; 669*48038c4aSMugunthan V N ti,max-div = <31>; 670*48038c4aSMugunthan V N ti,autoidle-shift = <8>; 671*48038c4aSMugunthan V N reg = <0x2db8>; 672*48038c4aSMugunthan V N ti,index-starts-at-one; 673*48038c4aSMugunthan V N ti,invert-autoidle-bit; 674*48038c4aSMugunthan V N }; 675*48038c4aSMugunthan V N 676*48038c4aSMugunthan V N dpll_per_clkdcoldo: dpll_per_clkdcoldo { 677*48038c4aSMugunthan V N #clock-cells = <0>; 678*48038c4aSMugunthan V N compatible = "ti,fixed-factor-clock"; 679*48038c4aSMugunthan V N clocks = <&dpll_per_ck>; 680*48038c4aSMugunthan V N ti,clock-mult = <1>; 681*48038c4aSMugunthan V N ti,clock-div = <1>; 682*48038c4aSMugunthan V N ti,autoidle-shift = <8>; 683*48038c4aSMugunthan V N reg = <0x2e14>; 684*48038c4aSMugunthan V N ti,invert-autoidle-bit; 685*48038c4aSMugunthan V N }; 686*48038c4aSMugunthan V N 687*48038c4aSMugunthan V N dll_aging_clk_div: dll_aging_clk_div { 688*48038c4aSMugunthan V N #clock-cells = <0>; 689*48038c4aSMugunthan V N compatible = "ti,divider-clock"; 690*48038c4aSMugunthan V N clocks = <&sys_clkin_ck>; 691*48038c4aSMugunthan V N reg = <0x4250>; 692*48038c4aSMugunthan V N ti,dividers = <8>, <16>, <32>; 693*48038c4aSMugunthan V N }; 694*48038c4aSMugunthan V N 695*48038c4aSMugunthan V N div_core_25m_ck: div_core_25m_ck { 696*48038c4aSMugunthan V N #clock-cells = <0>; 697*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 698*48038c4aSMugunthan V N clocks = <&sysclk_div>; 699*48038c4aSMugunthan V N clock-mult = <1>; 700*48038c4aSMugunthan V N clock-div = <8>; 701*48038c4aSMugunthan V N }; 702*48038c4aSMugunthan V N 703*48038c4aSMugunthan V N func_12m_clk: func_12m_clk { 704*48038c4aSMugunthan V N #clock-cells = <0>; 705*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 706*48038c4aSMugunthan V N clocks = <&dpll_per_m2_ck>; 707*48038c4aSMugunthan V N clock-mult = <1>; 708*48038c4aSMugunthan V N clock-div = <16>; 709*48038c4aSMugunthan V N }; 710*48038c4aSMugunthan V N 711*48038c4aSMugunthan V N vtp_clk_div: vtp_clk_div { 712*48038c4aSMugunthan V N #clock-cells = <0>; 713*48038c4aSMugunthan V N compatible = "fixed-factor-clock"; 714*48038c4aSMugunthan V N clocks = <&sys_clkin_ck>; 715*48038c4aSMugunthan V N clock-mult = <1>; 716*48038c4aSMugunthan V N clock-div = <2>; 717*48038c4aSMugunthan V N }; 718*48038c4aSMugunthan V N 719*48038c4aSMugunthan V N usbphy_32khz_clkmux: usbphy_32khz_clkmux { 720*48038c4aSMugunthan V N #clock-cells = <0>; 721*48038c4aSMugunthan V N compatible = "ti,mux-clock"; 722*48038c4aSMugunthan V N clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; 723*48038c4aSMugunthan V N reg = <0x4260>; 724*48038c4aSMugunthan V N }; 725*48038c4aSMugunthan V N 726*48038c4aSMugunthan V N usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k { 727*48038c4aSMugunthan V N #clock-cells = <0>; 728*48038c4aSMugunthan V N compatible = "ti,gate-clock"; 729*48038c4aSMugunthan V N clocks = <&usbphy_32khz_clkmux>; 730*48038c4aSMugunthan V N ti,bit-shift = <8>; 731*48038c4aSMugunthan V N reg = <0x2a40>; 732*48038c4aSMugunthan V N }; 733*48038c4aSMugunthan V N 734*48038c4aSMugunthan V N usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k { 735*48038c4aSMugunthan V N #clock-cells = <0>; 736*48038c4aSMugunthan V N compatible = "ti,gate-clock"; 737*48038c4aSMugunthan V N clocks = <&usbphy_32khz_clkmux>; 738*48038c4aSMugunthan V N ti,bit-shift = <8>; 739*48038c4aSMugunthan V N reg = <0x2a48>; 740*48038c4aSMugunthan V N }; 741*48038c4aSMugunthan V N 742*48038c4aSMugunthan V N usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m { 743*48038c4aSMugunthan V N #clock-cells = <0>; 744*48038c4aSMugunthan V N compatible = "ti,gate-clock"; 745*48038c4aSMugunthan V N clocks = <&dpll_per_clkdcoldo>; 746*48038c4aSMugunthan V N ti,bit-shift = <8>; 747*48038c4aSMugunthan V N reg = <0x8a60>; 748*48038c4aSMugunthan V N }; 749*48038c4aSMugunthan V N 750*48038c4aSMugunthan V N usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m { 751*48038c4aSMugunthan V N #clock-cells = <0>; 752*48038c4aSMugunthan V N compatible = "ti,gate-clock"; 753*48038c4aSMugunthan V N clocks = <&dpll_per_clkdcoldo>; 754*48038c4aSMugunthan V N ti,bit-shift = <8>; 755*48038c4aSMugunthan V N reg = <0x8a68>; 756*48038c4aSMugunthan V N }; 757*48038c4aSMugunthan V N}; 758