1*552a848eSStefano Babic /*
2*552a848eSStefano Babic * Copyright (C) 2016 Freescale Semiconductor, Inc.
3*552a848eSStefano Babic *
4*552a848eSStefano Babic * SPDX-License-Identifier: GPL-2.0+
5*552a848eSStefano Babic */
6*552a848eSStefano Babic #include <common.h>
7*552a848eSStefano Babic #include <asm/io.h>
8*552a848eSStefano Babic #include <asm/arch/imx-regs.h>
9*552a848eSStefano Babic #include <asm/mach-imx/rdc-sema.h>
10*552a848eSStefano Babic #include <asm/arch/imx-rdc.h>
11*552a848eSStefano Babic #include <linux/errno.h>
12*552a848eSStefano Babic
13*552a848eSStefano Babic /*
14*552a848eSStefano Babic * Check if the RDC Semaphore is required for this peripheral.
15*552a848eSStefano Babic */
imx_rdc_check_sema_required(int per_id)16*552a848eSStefano Babic static inline int imx_rdc_check_sema_required(int per_id)
17*552a848eSStefano Babic {
18*552a848eSStefano Babic struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
19*552a848eSStefano Babic u32 reg;
20*552a848eSStefano Babic
21*552a848eSStefano Babic reg = readl(&imx_rdc->pdap[per_id]);
22*552a848eSStefano Babic /*
23*552a848eSStefano Babic * No semaphore:
24*552a848eSStefano Babic * Intial value or this peripheral is assigned to only one domain
25*552a848eSStefano Babic */
26*552a848eSStefano Babic if (!(reg & RDC_PDAP_SREQ_MASK))
27*552a848eSStefano Babic return -ENOENT;
28*552a848eSStefano Babic
29*552a848eSStefano Babic return 0;
30*552a848eSStefano Babic }
31*552a848eSStefano Babic
32*552a848eSStefano Babic /*
33*552a848eSStefano Babic * Check the peripheral read / write access permission on Domain [dom_id].
34*552a848eSStefano Babic */
imx_rdc_check_permission(int per_id,int dom_id)35*552a848eSStefano Babic int imx_rdc_check_permission(int per_id, int dom_id)
36*552a848eSStefano Babic {
37*552a848eSStefano Babic struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
38*552a848eSStefano Babic u32 reg;
39*552a848eSStefano Babic
40*552a848eSStefano Babic reg = readl(&imx_rdc->pdap[per_id]);
41*552a848eSStefano Babic if (!(reg & RDC_PDAP_DRW_MASK(dom_id)))
42*552a848eSStefano Babic return -EACCES; /*No access*/
43*552a848eSStefano Babic
44*552a848eSStefano Babic return 0;
45*552a848eSStefano Babic }
46*552a848eSStefano Babic
47*552a848eSStefano Babic /*
48*552a848eSStefano Babic * Lock up the RDC semaphore for this peripheral if semaphore is required.
49*552a848eSStefano Babic */
imx_rdc_sema_lock(int per_id)50*552a848eSStefano Babic int imx_rdc_sema_lock(int per_id)
51*552a848eSStefano Babic {
52*552a848eSStefano Babic struct rdc_sema_regs *imx_rdc_sema;
53*552a848eSStefano Babic int ret;
54*552a848eSStefano Babic u8 reg;
55*552a848eSStefano Babic
56*552a848eSStefano Babic ret = imx_rdc_check_sema_required(per_id);
57*552a848eSStefano Babic if (ret)
58*552a848eSStefano Babic return ret;
59*552a848eSStefano Babic
60*552a848eSStefano Babic if (per_id < SEMA_GATES_NUM)
61*552a848eSStefano Babic imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
62*552a848eSStefano Babic else
63*552a848eSStefano Babic imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
64*552a848eSStefano Babic
65*552a848eSStefano Babic do {
66*552a848eSStefano Babic writeb(RDC_SEMA_PROC_ID,
67*552a848eSStefano Babic &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
68*552a848eSStefano Babic reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
69*552a848eSStefano Babic if ((reg & RDC_SEMA_GATE_GTFSM_MASK) == RDC_SEMA_PROC_ID)
70*552a848eSStefano Babic break; /* Get the Semaphore*/
71*552a848eSStefano Babic } while (1);
72*552a848eSStefano Babic
73*552a848eSStefano Babic return 0;
74*552a848eSStefano Babic }
75*552a848eSStefano Babic
76*552a848eSStefano Babic /*
77*552a848eSStefano Babic * Unlock the RDC semaphore for this peripheral if main CPU is the
78*552a848eSStefano Babic * semaphore owner.
79*552a848eSStefano Babic */
imx_rdc_sema_unlock(int per_id)80*552a848eSStefano Babic int imx_rdc_sema_unlock(int per_id)
81*552a848eSStefano Babic {
82*552a848eSStefano Babic struct rdc_sema_regs *imx_rdc_sema;
83*552a848eSStefano Babic int ret;
84*552a848eSStefano Babic u8 reg;
85*552a848eSStefano Babic
86*552a848eSStefano Babic ret = imx_rdc_check_sema_required(per_id);
87*552a848eSStefano Babic if (ret)
88*552a848eSStefano Babic return ret;
89*552a848eSStefano Babic
90*552a848eSStefano Babic if (per_id < SEMA_GATES_NUM)
91*552a848eSStefano Babic imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
92*552a848eSStefano Babic else
93*552a848eSStefano Babic imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
94*552a848eSStefano Babic
95*552a848eSStefano Babic reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
96*552a848eSStefano Babic if ((reg & RDC_SEMA_GATE_GTFSM_MASK) != RDC_SEMA_PROC_ID)
97*552a848eSStefano Babic return -EACCES; /*Not the semaphore owner */
98*552a848eSStefano Babic
99*552a848eSStefano Babic writeb(0x0, &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
100*552a848eSStefano Babic
101*552a848eSStefano Babic return 0;
102*552a848eSStefano Babic }
103*552a848eSStefano Babic
104*552a848eSStefano Babic /*
105*552a848eSStefano Babic * Setup RDC setting for one peripheral
106*552a848eSStefano Babic */
imx_rdc_setup_peri(rdc_peri_cfg_t p)107*552a848eSStefano Babic int imx_rdc_setup_peri(rdc_peri_cfg_t p)
108*552a848eSStefano Babic {
109*552a848eSStefano Babic struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
110*552a848eSStefano Babic u32 reg = 0;
111*552a848eSStefano Babic u32 share_count = 0;
112*552a848eSStefano Babic u32 peri_id = p & RDC_PERI_MASK;
113*552a848eSStefano Babic u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
114*552a848eSStefano Babic
115*552a848eSStefano Babic /* No domain assigned */
116*552a848eSStefano Babic if (domain == 0)
117*552a848eSStefano Babic return -EINVAL;
118*552a848eSStefano Babic
119*552a848eSStefano Babic reg |= domain;
120*552a848eSStefano Babic
121*552a848eSStefano Babic share_count = (domain & 0x3)
122*552a848eSStefano Babic + ((domain >> 2) & 0x3)
123*552a848eSStefano Babic + ((domain >> 4) & 0x3)
124*552a848eSStefano Babic + ((domain >> 6) & 0x3);
125*552a848eSStefano Babic
126*552a848eSStefano Babic if (share_count > 0x3)
127*552a848eSStefano Babic reg |= RDC_PDAP_SREQ_MASK;
128*552a848eSStefano Babic
129*552a848eSStefano Babic writel(reg, &imx_rdc->pdap[peri_id]);
130*552a848eSStefano Babic
131*552a848eSStefano Babic return 0;
132*552a848eSStefano Babic }
133*552a848eSStefano Babic
134*552a848eSStefano Babic /*
135*552a848eSStefano Babic * Setup RDC settings for multiple peripherals
136*552a848eSStefano Babic */
imx_rdc_setup_peripherals(rdc_peri_cfg_t const * peripherals_list,unsigned count)137*552a848eSStefano Babic int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
138*552a848eSStefano Babic unsigned count)
139*552a848eSStefano Babic {
140*552a848eSStefano Babic rdc_peri_cfg_t const *p = peripherals_list;
141*552a848eSStefano Babic int i, ret;
142*552a848eSStefano Babic
143*552a848eSStefano Babic for (i = 0; i < count; i++) {
144*552a848eSStefano Babic ret = imx_rdc_setup_peri(*p);
145*552a848eSStefano Babic if (ret)
146*552a848eSStefano Babic return ret;
147*552a848eSStefano Babic p++;
148*552a848eSStefano Babic }
149*552a848eSStefano Babic
150*552a848eSStefano Babic return 0;
151*552a848eSStefano Babic }
152*552a848eSStefano Babic
153*552a848eSStefano Babic /*
154*552a848eSStefano Babic * Setup RDC setting for one master
155*552a848eSStefano Babic */
imx_rdc_setup_ma(rdc_ma_cfg_t p)156*552a848eSStefano Babic int imx_rdc_setup_ma(rdc_ma_cfg_t p)
157*552a848eSStefano Babic {
158*552a848eSStefano Babic struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
159*552a848eSStefano Babic u32 master_id = (p & RDC_MASTER_MASK) >> RDC_MASTER_SHIFT;
160*552a848eSStefano Babic u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
161*552a848eSStefano Babic
162*552a848eSStefano Babic writel((domain & RDC_MDA_DID_MASK), &imx_rdc->mda[master_id]);
163*552a848eSStefano Babic
164*552a848eSStefano Babic return 0;
165*552a848eSStefano Babic }
166*552a848eSStefano Babic
167*552a848eSStefano Babic /*
168*552a848eSStefano Babic * Setup RDC settings for multiple masters
169*552a848eSStefano Babic */
imx_rdc_setup_masters(rdc_ma_cfg_t const * masters_list,unsigned count)170*552a848eSStefano Babic int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count)
171*552a848eSStefano Babic {
172*552a848eSStefano Babic rdc_ma_cfg_t const *p = masters_list;
173*552a848eSStefano Babic int i, ret;
174*552a848eSStefano Babic
175*552a848eSStefano Babic for (i = 0; i < count; i++) {
176*552a848eSStefano Babic ret = imx_rdc_setup_ma(*p);
177*552a848eSStefano Babic if (ret)
178*552a848eSStefano Babic return ret;
179*552a848eSStefano Babic p++;
180*552a848eSStefano Babic }
181*552a848eSStefano Babic
182*552a848eSStefano Babic return 0;
183*552a848eSStefano Babic }
184