| /rk3399_rockchip-uboot/arch/x86/include/asm/arch-quark/ |
| H A D | msg_port.h | 109 #define msg_port_generic_clrsetbits(type, port, reg, clr, set) \ argument
112 & ~(clr)) | (set))
114 #define msg_port_clrbits(port, reg, clr) \ argument
115 msg_port_generic_clrsetbits(normal, port, reg, clr, 0)
118 #define msg_port_clrsetbits(port, reg, clr, set) \ argument
119 msg_port_generic_clrsetbits(normal, port, reg, clr, set)
121 #define msg_port_alt_clrbits(port, reg, clr) \ argument
122 msg_port_generic_clrsetbits(alt, port, reg, clr, 0)
125 #define msg_port_alt_clrsetbits(port, reg, clr, set) \ argument
126 msg_port_generic_clrsetbits(alt, port, reg, clr, set)
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | hardware.h | 10 #define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | (set)) argument
12 #define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) argument
16 #define rk_clrsetreg(addr, clr, set) \ argument
17 writel((((clr) | (set)) << 16) | (set), addr)
18 #define rk_clrreg(addr, clr) writel((clr) << 16, addr) argument
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| /rk3399_rockchip-uboot/board/samsung/odroid/ |
| H A D | odroid.c | 96 unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc; in board_clock_init() local
152 clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) | in board_clock_init()
156 clrsetbits_le32(&clk->div_cpu0, clr, set); in board_clock_init()
168 clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7); in board_clock_init()
171 clrsetbits_le32(&clk->div_cpu1, clr, set); in board_clock_init()
224 clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) | in board_clock_init()
241 clrsetbits_le32(&clk->div_dmc0, clr, set); in board_clock_init()
248 clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) | in board_clock_init()
264 clrsetbits_le32(&clk->div_dmc1, clr, set); in board_clock_init()
271 clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) | in board_clock_init()
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| /rk3399_rockchip-uboot/drivers/net/ |
| H A D | pic32_eth.c | 64 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_mii_init()
78 writel(EMAC_SOFTRESET, &emac_p->cfg1.clr); /* reset deassert */ in pic32_mii_init()
84 writel(EMAC_RMII_RESET, &emac_p->supp.clr); in pic32_mii_init()
142 writel(EMAC_FULLDUP, &emac_p->cfg2.clr); in pic32_mac_adjust_link()
151 writel(EMAC_RMII_SPD100, &emac_p->supp.clr); in pic32_mac_adjust_link()
197 writel(EMAC_RMII_SPD100, &emac_p->supp.clr); in pic32_mac_init()
239 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_ctrl_reset()
249 writel(0xffffffff, &ectl_p->irq.clr); in pic32_ctrl_reset()
252 writel(0xffffffff, &ectl_p->txst.clr); in pic32_ctrl_reset()
253 writel(0xffffffff, &ectl_p->rxst.clr); in pic32_ctrl_reset()
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| /rk3399_rockchip-uboot/drivers/video/ |
| H A D | console_rotate.c | 15 static int console_set_row_1(struct udevice *dev, uint row, int clr) in console_set_row_1() argument
31 *dst++ = clr; in console_set_row_1()
40 *dst++ = clr; in console_set_row_1()
49 *dst++ = clr; in console_set_row_1()
147 static int console_set_row_2(struct udevice *dev, uint row, int clr) in console_set_row_2() argument
162 *dst++ = clr; in console_set_row_2()
171 *dst++ = clr; in console_set_row_2()
180 *dst++ = clr; in console_set_row_2()
274 static int console_set_row_3(struct udevice *dev, uint row, int clr) in console_set_row_3() argument
289 *dst++ = clr; in console_set_row_3()
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| H A D | console_normal.c | 17 static int console_normal_set_row(struct udevice *dev, uint row, int clr) in console_normal_set_row() argument
31 *dst++ = clr; in console_normal_set_row()
40 *dst++ = clr; in console_normal_set_row()
49 *dst++ = clr; in console_normal_set_row()
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| H A D | console_truetype.c | 125 static int console_truetype_set_row(struct udevice *dev, uint row, int clr) in console_truetype_set_row() argument
140 *dst++ = clr; in console_truetype_set_row()
149 *dst++ = clr; in console_truetype_set_row()
158 *dst++ = clr; in console_truetype_set_row()
318 int xend, int yend, int clr) in console_truetype_erase() argument
334 *dst++ = clr; in console_truetype_erase()
343 *dst++ = clr; in console_truetype_erase()
352 *dst++ = clr; in console_truetype_erase()
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| H A D | vidconsole-uclass.c | 41 int vidconsole_set_row(struct udevice *dev, uint row, int clr) in vidconsole_set_row() argument
47 return ops->set_row(dev, row, clr); in vidconsole_set_row()
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| /rk3399_rockchip-uboot/common/ |
| H A D | lcd_console_rotation.c | 32 static inline void console_setrow90(struct console_t *pcons, u32 row, int clr) in console_setrow90() argument
41 *dst-- = clr; in console_setrow90()
87 static inline void console_setrow180(struct console_t *pcons, u32 row, int clr) in console_setrow180() argument
95 *dst++ = clr; in console_setrow180()
134 static inline void console_setrow270(struct console_t *pcons, u32 row, int clr) in console_setrow270() argument
142 *dst++ = clr; in console_setrow270()
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| H A D | lcd_console.c | 64 static inline void console_setrow0(struct console_t *pcons, u32 row, int clr) in console_setrow0() argument
72 *dst++ = clr; in console_setrow0()
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| /rk3399_rockchip-uboot/drivers/gpio/ |
| H A D | pic32_gpio.c | 58 writel(mask, &priv->regs->port.clr); in pic32_gpio_set_value()
82 writel(mask, &priv->regs->ansel.clr); in pic32_gpio_direction_input()
94 writel(mask, &priv->regs->ansel.clr); in pic32_gpio_direction_output()
95 writel(mask, &priv->regs->tris.clr); in pic32_gpio_direction_output()
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| /rk3399_rockchip-uboot/drivers/spi/ |
| H A D | bcm63xx_hsspi.c | 145 uint32_t clr, set; in bcm63xx_hsspi_activate_cs() local
156 clr = SPI_PFL_SIG_LAUNCHRIS_MASK | in bcm63xx_hsspi_activate_cs()
170 clrsetbits_be32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set); in bcm63xx_hsspi_activate_cs()
174 clr = 0; in bcm63xx_hsspi_activate_cs()
178 clr |= BIT(plat->cs); in bcm63xx_hsspi_activate_cs()
184 clr |= BIT(!plat->cs); in bcm63xx_hsspi_activate_cs()
188 clrsetbits_be32(priv->regs + SPI_CTL_REG, clr, set); in bcm63xx_hsspi_activate_cs()
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| /rk3399_rockchip-uboot/include/ |
| H A D | video_console.h | 91 int (*set_row)(struct udevice *dev, uint row, int clr);
159 int vidconsole_set_row(struct udevice *dev, uint row, int clr);
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| H A D | lcd_console.h | 17 void (*fp_console_setrow)(struct console_t *pcons, u32 row, int clr);
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| /rk3399_rockchip-uboot/drivers/mmc/ |
| H A D | ftsdc010_mci.c | 57 ®s->clr); in ftsdc010_send_cmd()
64 writel(FTSDC010_STATUS_CMD_SEND, ®s->clr); in ftsdc010_send_cmd()
73 writel(st & FTSDC010_STATUS_RSP_MASK, ®s->clr); in ftsdc010_send_cmd()
136 writel(st & mask, ®s->clr); in ftsdc010_wait()
178 | FTSDC010_STATUS_FIFO_ORUN, ®s->clr); in ftsdc010_request()
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| /rk3399_rockchip-uboot/drivers/misc/ |
| H A D | smsc_sio1007.c | 25 static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set) in sio1007_clrsetbits() argument
27 sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set); in sio1007_clrsetbits()
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| /rk3399_rockchip-uboot/arch/mips/mach-pic32/include/mach/ |
| H A D | pic32.h | 62 u32 clr; member
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| /rk3399_rockchip-uboot/drivers/power/pmic/ |
| H A D | pmic-uclass.c | 179 int pmic_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set) in pmic_clrsetbits() argument
187 byte = (ret & ~clr) | set; in pmic_clrsetbits()
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| /rk3399_rockchip-uboot/arch/mips/include/asm/ |
| H A D | io.h | 516 static inline void clrbits_##sfx(volatile void __iomem *mem, type clr) \
520 __val &= ~clr; \
539 type clr, type set) \
543 __val &= ~clr; \
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| /rk3399_rockchip-uboot/drivers/pci/ |
| H A D | pci-uclass.c | 409 u32 clr, u32 set) in pci_bus_clrset_config32() argument
417 val &= ~clr; in pci_bus_clrset_config32()
590 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set) in dm_pci_clrset_config8() argument
598 val &= ~clr; in dm_pci_clrset_config8()
604 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set) in dm_pci_clrset_config16() argument
612 val &= ~clr; in dm_pci_clrset_config16()
618 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set) in dm_pci_clrset_config32() argument
626 val &= ~clr; in dm_pci_clrset_config32()
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| /rk3399_rockchip-uboot/drivers/pinctrl/ |
| H A D | pinctrl_pic32.c | 144 writel(BIT(pin), &port->ansel.clr); in pic32_pinconfig_one()
153 writel(BIT(pin), &port->tris.clr); in pic32_pinconfig_one()
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| /rk3399_rockchip-uboot/arch/m68k/cpu/mcf5445x/ |
| H A D | start.S | 133 clr.l %sp@-
160 clr.l %sp@-
509 clr.l %sp@-
565 clr.l (%a1)+
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| /rk3399_rockchip-uboot/include/faraday/ |
| H A D | ftsdc010.h | 28 unsigned int clr; /* 0x2c - clear reg */ member
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| /rk3399_rockchip-uboot/arch/m68k/cpu/mcf547x_8x/ |
| H A D | start.S | 149 clr.l %sp@-
204 clr.l (%a1)+
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| /rk3399_rockchip-uboot/arch/m68k/cpu/mcf530x/ |
| H A D | start.S | 151 clr.l %sp@-
200 clr.l (%a1)+
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