132c1a6eeSPurna Chandra Mandal /* 232c1a6eeSPurna Chandra Mandal * (c) 2015 Paul Thacker <paul.thacker@microchip.com> 332c1a6eeSPurna Chandra Mandal * 432c1a6eeSPurna Chandra Mandal * SPDX-License-Identifier: GPL-2.0+ 532c1a6eeSPurna Chandra Mandal * 632c1a6eeSPurna Chandra Mandal */ 732c1a6eeSPurna Chandra Mandal 832c1a6eeSPurna Chandra Mandal #ifndef __PIC32_REGS_H__ 932c1a6eeSPurna Chandra Mandal #define __PIC32_REGS_H__ 1032c1a6eeSPurna Chandra Mandal 1132c1a6eeSPurna Chandra Mandal #include <asm/io.h> 1232c1a6eeSPurna Chandra Mandal 1332c1a6eeSPurna Chandra Mandal /* System Configuration */ 1432c1a6eeSPurna Chandra Mandal #define PIC32_CFG_BASE 0x1f800000 1532c1a6eeSPurna Chandra Mandal 1632c1a6eeSPurna Chandra Mandal /* System config register offsets */ 1732c1a6eeSPurna Chandra Mandal #define CFGCON 0x0000 1832c1a6eeSPurna Chandra Mandal #define DEVID 0x0020 1932c1a6eeSPurna Chandra Mandal #define SYSKEY 0x0030 2032c1a6eeSPurna Chandra Mandal #define PMD1 0x0040 2132c1a6eeSPurna Chandra Mandal #define PMD7 0x00a0 2232c1a6eeSPurna Chandra Mandal #define CFGEBIA 0x00c0 2332c1a6eeSPurna Chandra Mandal #define CFGEBIC 0x00d0 2432c1a6eeSPurna Chandra Mandal #define CFGPG 0x00e0 2532c1a6eeSPurna Chandra Mandal #define CFGMPLL 0x0100 2632c1a6eeSPurna Chandra Mandal 2732c1a6eeSPurna Chandra Mandal /* Non Volatile Memory (NOR flash) */ 2832c1a6eeSPurna Chandra Mandal #define PIC32_NVM_BASE (PIC32_CFG_BASE + 0x0600) 2932c1a6eeSPurna Chandra Mandal /* Oscillator Configuration */ 3032c1a6eeSPurna Chandra Mandal #define PIC32_OSC_BASE (PIC32_CFG_BASE + 0x1200) 3132c1a6eeSPurna Chandra Mandal /* Peripheral Pin Select Input */ 3232c1a6eeSPurna Chandra Mandal #define PPS_IN_BASE 0x1f801400 3332c1a6eeSPurna Chandra Mandal /* Peripheral Pin Select Output */ 3432c1a6eeSPurna Chandra Mandal #define PPS_OUT_BASE 0x1f801500 3532c1a6eeSPurna Chandra Mandal /* Pin Config */ 3632c1a6eeSPurna Chandra Mandal #define PINCTRL_BASE 0x1f860000 3732c1a6eeSPurna Chandra Mandal 3832c1a6eeSPurna Chandra Mandal /* USB Core */ 3932c1a6eeSPurna Chandra Mandal #define PIC32_USB_CORE_BASE 0x1f8e3000 4032c1a6eeSPurna Chandra Mandal #define PIC32_USB_CTRL_BASE 0x1f884000 4132c1a6eeSPurna Chandra Mandal 4232c1a6eeSPurna Chandra Mandal /* SPI1-SPI6 */ 4332c1a6eeSPurna Chandra Mandal #define PIC32_SPI1_BASE 0x1f821000 4432c1a6eeSPurna Chandra Mandal 4532c1a6eeSPurna Chandra Mandal /* Prefetch Module */ 4632c1a6eeSPurna Chandra Mandal #define PREFETCH_BASE 0x1f8e0000 4732c1a6eeSPurna Chandra Mandal 4832c1a6eeSPurna Chandra Mandal /* DDR2 Controller */ 4932c1a6eeSPurna Chandra Mandal #define PIC32_DDR2C_BASE 0x1f8e8000 5032c1a6eeSPurna Chandra Mandal 5132c1a6eeSPurna Chandra Mandal /* DDR2 PHY */ 5232c1a6eeSPurna Chandra Mandal #define PIC32_DDR2P_BASE 0x1f8e9100 5332c1a6eeSPurna Chandra Mandal 5432c1a6eeSPurna Chandra Mandal /* EBI */ 5532c1a6eeSPurna Chandra Mandal #define PIC32_EBI_BASE 0x1f8e1000 5632c1a6eeSPurna Chandra Mandal 5732c1a6eeSPurna Chandra Mandal /* SQI */ 5832c1a6eeSPurna Chandra Mandal #define PIC32_SQI_BASE 0x1f8e2000 5932c1a6eeSPurna Chandra Mandal 6032c1a6eeSPurna Chandra Mandal struct pic32_reg_atomic { 6132c1a6eeSPurna Chandra Mandal u32 raw; 6232c1a6eeSPurna Chandra Mandal u32 clr; 6332c1a6eeSPurna Chandra Mandal u32 set; 6432c1a6eeSPurna Chandra Mandal u32 inv; 6532c1a6eeSPurna Chandra Mandal }; 6632c1a6eeSPurna Chandra Mandal 6732c1a6eeSPurna Chandra Mandal #define _CLR_OFFSET 0x04 6832c1a6eeSPurna Chandra Mandal #define _SET_OFFSET 0x08 6932c1a6eeSPurna Chandra Mandal #define _INV_OFFSET 0x0c 7032c1a6eeSPurna Chandra Mandal pic32_get_syscfg_base(void)7132c1a6eeSPurna Chandra Mandalstatic inline void __iomem *pic32_get_syscfg_base(void) 7232c1a6eeSPurna Chandra Mandal { 7332c1a6eeSPurna Chandra Mandal return (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE); 7432c1a6eeSPurna Chandra Mandal } 7532c1a6eeSPurna Chandra Mandal 76*be961fa1SPurna Chandra Mandal /* Core */ 77*be961fa1SPurna Chandra Mandal const char *get_core_name(void); 78*be961fa1SPurna Chandra Mandal 7932c1a6eeSPurna Chandra Mandal #endif /* __PIC32_REGS_H__ */ 80