| /rk3399_rockchip-uboot/board/aristainetos/ |
| H A D | axi.cfg | 20 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /rk3399_rockchip-uboot/board/advantech/dms-ba16/ |
| H A D | clocks.cfg | 12 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /rk3399_rockchip-uboot/arch/arm/dts/ |
| H A D | dra72-evm-tps65917.dtsi | 89 regulator-allow-bypass;
96 regulator-allow-bypass;
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| H A D | omap34xx-omap36xx-clocks.dtsi | 173 ti,low-power-bypass;
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| /rk3399_rockchip-uboot/arch/arm/mach-socfpga/include/mach/ |
| H A D | clock_manager_arria10.h | 18 u32 bypass; member
45 u32 bypass; member
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| H A D | clock_manager_gen5.h | 102 u32 bypass; member
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| /rk3399_rockchip-uboot/board/tqc/tqma6/ |
| H A D | clocks.cfg | 22 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra20/ |
| H A D | warmboot_avp.c | 176 pllx_base.bypass = 1; in wb_start()
193 pllx_base.bypass = 0; in wb_start()
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| /rk3399_rockchip-uboot/drivers/spi/ |
| H A D | cadence_qspi.h | 79 unsigned int bypass, unsigned int delay);
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| H A D | cadence_qspi_apb.c | 230 unsigned int bypass, unsigned int delay) in cadence_qspi_apb_readdata_capture() argument
237 if (bypass) in cadence_qspi_apb_readdata_capture()
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| /rk3399_rockchip-uboot/board/toradex/apalis_imx6/ |
| H A D | clocks.cfg | 29 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /rk3399_rockchip-uboot/board/toradex/colibri_imx6/ |
| H A D | clocks.cfg | 29 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /rk3399_rockchip-uboot/board/boundary/nitrogen6x/ |
| H A D | clocks.cfg | 28 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra/ |
| H A D | warmboot.h | 82 u32 bypass:1; member
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| /rk3399_rockchip-uboot/doc/ |
| H A D | README.ag101p | 22 If you want to boot this system from SPI ROM and bypass e-bios (the
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| /rk3399_rockchip-uboot/drivers/clk/ |
| H A D | clk_zynq.c | 134 u32 clk_ctrl, reset, pwrdwn, mul, bypass; in zynq_clk_get_pll_rate() local
143 bypass = clk_ctrl & PLLCTRL_BPFORCE_MASK; in zynq_clk_get_pll_rate()
144 if (bypass) in zynq_clk_get_pll_rate()
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| /rk3399_rockchip-uboot/drivers/video/drm/rk628/ |
| H A D | rk628_cru.c | 62 u32 postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass; in rk628_cru_clk_get_rate_pll() local
98 bypass = (con0 & PLL_BYPASS_MASK) >> PLL_BYPASS_SHIFT; in rk628_cru_clk_get_rate_pll()
106 if (bypass) in rk628_cru_clk_get_rate_pll()
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| /rk3399_rockchip-uboot/board/freescale/mx6qarm2/ |
| H A D | imximage.cfg | 207 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
334 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /rk3399_rockchip-uboot/drivers/rkflash/ |
| H A D | nandc.h | 123 unsigned bypass : 1; member
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| /rk3399_rockchip-uboot/board/logicpd/imx6/ |
| H A D | mx6q_2x_MT41K512M16HA.cfg | 110 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /rk3399_rockchip-uboot/board/ge/bx50v3/ |
| H A D | bx50v3.cfg | 138 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /rk3399_rockchip-uboot/board/seco/mx6quq7/ |
| H A D | mx6quq7-2g.cfg | 170 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /rk3399_rockchip-uboot/board/barco/titanium/ |
| H A D | imximage.cfg | 165 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/ |
| H A D | display.h | 15 u32 bypass; /* 0x008 */ member
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| /rk3399_rockchip-uboot/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 23 writel(val, &clock_manager_base->bypass); in cm_write_bypass()
|