1*f9162b15SAkshay Bhat/* 2*f9162b15SAkshay Bhat * 3*f9162b15SAkshay Bhat * Copyright 2015 Timesys Corporation. 4*f9162b15SAkshay Bhat * Copyright 2015 General Electric Company 5*f9162b15SAkshay Bhat * 6*f9162b15SAkshay Bhat * SPDX-License-Identifier: GPL-2.0+ 7*f9162b15SAkshay Bhat * 8*f9162b15SAkshay Bhat * Refer doc/README.imximage for more details about how-to configure 9*f9162b15SAkshay Bhat * and create imximage boot image 10*f9162b15SAkshay Bhat * 11*f9162b15SAkshay Bhat * The syntax is taken as close as possible with the kwbimage 12*f9162b15SAkshay Bhat */ 13*f9162b15SAkshay Bhat 14*f9162b15SAkshay BhatIMAGE_VERSION 2 15*f9162b15SAkshay BhatBOOT_FROM sd 16*f9162b15SAkshay Bhat 17*f9162b15SAkshay Bhat#define __ASSEMBLY__ 18*f9162b15SAkshay Bhat#include <config.h> 19*f9162b15SAkshay Bhat#include "asm/arch/mx6-ddr.h" 20*f9162b15SAkshay Bhat#include "asm/arch/iomux.h" 21*f9162b15SAkshay Bhat#include "asm/arch/crm_regs.h" 22*f9162b15SAkshay Bhat 23*f9162b15SAkshay Bhat/* DDR IO */ 24*f9162b15SAkshay BhatDATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000 25*f9162b15SAkshay BhatDATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 26*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 27*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 28*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_CAS, 0x00000030 29*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_RAS, 0x00000030 30*f9162b15SAkshay BhatDATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 31*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_RESET, 0x00000030 32*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 33*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030 34*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030 35*f9162b15SAkshay BhatDATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 36*f9162b15SAkshay BhatDATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 37*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 38*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 39*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 40*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 41*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 42*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 43*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 44*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 45*f9162b15SAkshay BhatDATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 46*f9162b15SAkshay BhatDATA 4, MX6_IOM_GRP_B0DS, 0x00000030 47*f9162b15SAkshay BhatDATA 4, MX6_IOM_GRP_B1DS, 0x00000030 48*f9162b15SAkshay BhatDATA 4, MX6_IOM_GRP_B2DS, 0x00000030 49*f9162b15SAkshay BhatDATA 4, MX6_IOM_GRP_B3DS, 0x00000030 50*f9162b15SAkshay BhatDATA 4, MX6_IOM_GRP_B4DS, 0x00000030 51*f9162b15SAkshay BhatDATA 4, MX6_IOM_GRP_B5DS, 0x00000030 52*f9162b15SAkshay BhatDATA 4, MX6_IOM_GRP_B6DS, 0x00000030 53*f9162b15SAkshay BhatDATA 4, MX6_IOM_GRP_B7DS, 0x00000030 54*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 55*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 56*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 57*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 58*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 59*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 60*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 61*f9162b15SAkshay BhatDATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 62*f9162b15SAkshay Bhat 63*f9162b15SAkshay Bhat/* Calibrations */ 64*f9162b15SAkshay Bhat/* ZQ */ 65*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 66*f9162b15SAkshay Bhat/* write leveling */ 67*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F 68*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F 69*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F 70*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F 71*f9162b15SAkshay Bhat/* Read DQS Gating calibration */ 72*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x45380544 73*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x05280530 74*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4530053C 75*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0530050C 76*f9162b15SAkshay Bhat/* Read calibration */ 77*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x36303032 78*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38363042 79*f9162b15SAkshay Bhat/* Write calibration */ 80*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A3A423E 81*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A38483E 82*f9162b15SAkshay Bhat/* read data bit delay */ 83*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 84*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 85*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 86*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 87*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 88*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 89*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 90*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 91*f9162b15SAkshay Bhat 92*f9162b15SAkshay Bhat/* Complete calibration by forced measurment */ 93*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 94*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 95*f9162b15SAkshay Bhat 96*f9162b15SAkshay Bhat/* MMDC init */ 97*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 98*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 99*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDCFG0, 0x8A8F79A4 100*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538E64 101*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db 102*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 103*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 104*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 105*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDOR, 0x008F1023 106*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDASP, 0x00000047 107*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDCTL, 0x841a0000 108*f9162b15SAkshay Bhat 109*f9162b15SAkshay Bhat/* Initialize Micron MT41J128M */ 110*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 111*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR, 0x0408803a 112*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 113*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b 114*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR, 0x00408031 115*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR, 0x00408039 116*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 117*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 118*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 119*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 120*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDREF, 0x00005800 121*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 122*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 123*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 124*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 125*f9162b15SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 126*f9162b15SAkshay Bhat 127*f9162b15SAkshay Bhat/* set the default clock gate to save power */ 128*f9162b15SAkshay BhatDATA 4, CCM_CCGR0, 0x00C03F3F 129*f9162b15SAkshay BhatDATA 4, CCM_CCGR1, 0x0030FC03 130*f9162b15SAkshay BhatDATA 4, CCM_CCGR2, 0x0FFFC000 131*f9162b15SAkshay BhatDATA 4, CCM_CCGR3, 0x3FF00000 132*f9162b15SAkshay BhatDATA 4, CCM_CCGR4, 0x00FFF300 133*f9162b15SAkshay BhatDATA 4, CCM_CCGR5, 0x0F0000C3 134*f9162b15SAkshay BhatDATA 4, CCM_CCGR6, 0x000003FF 135*f9162b15SAkshay Bhat 136*f9162b15SAkshay Bhat/* enable AXI cache for VDOA/VPU/IPU */ 137*f9162b15SAkshay BhatDATA 4, MX6_IOMUXC_GPR4, 0xF00000CF 138*f9162b15SAkshay Bhat/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 139*f9162b15SAkshay BhatDATA 4, MX6_IOMUXC_GPR6, 0x007F007F 140*f9162b15SAkshay BhatDATA 4, MX6_IOMUXC_GPR7, 0x007F007F 141*f9162b15SAkshay Bhat 142*f9162b15SAkshay Bhat/* 143*f9162b15SAkshay Bhat * Setup CCM_CCOSR register as follows: 144*f9162b15SAkshay Bhat * 145*f9162b15SAkshay Bhat * cko1_en 1 --> CKO1 enabled 146*f9162b15SAkshay Bhat * cko1_div 111 --> divide by 8 147*f9162b15SAkshay Bhat * cko1_sel 1011 --> ahb_clk_root 148*f9162b15SAkshay Bhat * 149*f9162b15SAkshay Bhat * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz 150*f9162b15SAkshay Bhat */ 151*f9162b15SAkshay BhatDATA 4, CCM_CCOSR, 0x000000fb 152