1ba0501acSDingqiang Lin /* 2ba0501acSDingqiang Lin * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3ba0501acSDingqiang Lin * 4ba0501acSDingqiang Lin * SPDX-License-Identifier: GPL-2.0 5ba0501acSDingqiang Lin */ 6ba0501acSDingqiang Lin 7ba0501acSDingqiang Lin #ifndef __NAND_H 8ba0501acSDingqiang Lin #define __NAND_H 9ba0501acSDingqiang Lin 10ba0501acSDingqiang Lin #include <asm/io.h> 11ba0501acSDingqiang Lin 12ba0501acSDingqiang Lin #define nandc_writel(v, offs) writel((v), (offs) + nandc_base) 13ba0501acSDingqiang Lin #define nandc_readl(offs) readl((offs) + nandc_base) 14ba0501acSDingqiang Lin 15ba0501acSDingqiang Lin #define NANDC_READ 0 16ba0501acSDingqiang Lin #define NANDC_WRITE 1 1727ffef75SDingqiang Lin #define RK3326_NANDC_VER 0x56393030 18ba0501acSDingqiang Lin 19ba0501acSDingqiang Lin /* INT ID */ 20ba0501acSDingqiang Lin enum NANDC_IRQ_NUM_T { 21ba0501acSDingqiang Lin NC_IRQ_DMA = 0, 22ba0501acSDingqiang Lin NC_IRQ_FRDY, 23ba0501acSDingqiang Lin NC_IRQ_BCHERR, 24ba0501acSDingqiang Lin NC_IRQ_BCHFAIL, 25ba0501acSDingqiang Lin NC_IRQ_LLP 26ba0501acSDingqiang Lin }; 27ba0501acSDingqiang Lin 2827ffef75SDingqiang Lin enum ENUM_NANDC_BCH_CFG { 2927ffef75SDingqiang Lin NC_BCH_70 = 0, 3027ffef75SDingqiang Lin NC_BCH_24, 3127ffef75SDingqiang Lin NC_BCH_40, 3227ffef75SDingqiang Lin NC_BCH_60, 3327ffef75SDingqiang Lin }; 3427ffef75SDingqiang Lin 35ba0501acSDingqiang Lin union FM_CTL_T { 36ba0501acSDingqiang Lin u32 d32; 37ba0501acSDingqiang Lin struct { 38ba0501acSDingqiang Lin unsigned cs : 8; /* bits[0:7] */ 39ba0501acSDingqiang Lin unsigned wp : 1; /* bits[8] */ 40ba0501acSDingqiang Lin unsigned rdy : 1; /* bits[9] */ 41ba0501acSDingqiang Lin unsigned fifo_empty : 1; /* bits[10] */ 42ba0501acSDingqiang Lin unsigned reserved11 : 1; /* bits[11] */ 43ba0501acSDingqiang Lin unsigned dwidth : 1; /* bits[12] */ 44ba0501acSDingqiang Lin unsigned tm : 1; /* bits[13] */ 45ba0501acSDingqiang Lin unsigned onficlk_en : 1; /* bits[14] */ 46ba0501acSDingqiang Lin unsigned toggle_en : 1; /* bits[15] */ 47ba0501acSDingqiang Lin unsigned flash_abort_en : 1; /* bits[16] */ 48ba0501acSDingqiang Lin unsigned flash_abort_clear : 1; /* bits[17] */ 49ba0501acSDingqiang Lin unsigned reserved18_23 : 6; /* bits[18:23] */ 50ba0501acSDingqiang Lin unsigned read_delay : 3; /* bits[24:26] */ 51ba0501acSDingqiang Lin unsigned reserved27_31 : 5; /* bits[27:31] */ 52ba0501acSDingqiang Lin } V6; 5327ffef75SDingqiang Lin struct { 5427ffef75SDingqiang Lin unsigned cs : 8; 5527ffef75SDingqiang Lin unsigned wp : 1; 5627ffef75SDingqiang Lin unsigned frdy : 1; 5727ffef75SDingqiang Lin unsigned fifo_empth_flash : 1; 5827ffef75SDingqiang Lin unsigned reserved11_12 : 2; 5927ffef75SDingqiang Lin unsigned tm : 1; 6027ffef75SDingqiang Lin unsigned syn_clken : 1; 6127ffef75SDingqiang Lin unsigned syn_mode : 1; 6227ffef75SDingqiang Lin unsigned flash_abort_en : 1; 6327ffef75SDingqiang Lin unsigned flash_abort_clear : 1; 6427ffef75SDingqiang Lin unsigned sif_read_delay : 3; 6527ffef75SDingqiang Lin unsigned io_mux : 3; 6627ffef75SDingqiang Lin unsigned reserved24_31 : 8; 6727ffef75SDingqiang Lin } V9; 68ba0501acSDingqiang Lin }; 69ba0501acSDingqiang Lin 70ba0501acSDingqiang Lin union FM_WAIT_T { 71ba0501acSDingqiang Lin u32 d32; 72ba0501acSDingqiang Lin struct { 73ba0501acSDingqiang Lin unsigned csrw : 5; 74ba0501acSDingqiang Lin unsigned rwpw : 6; 75ba0501acSDingqiang Lin unsigned rdy : 1; 76ba0501acSDingqiang Lin unsigned rwcs : 6; 77ba0501acSDingqiang Lin unsigned reserved18_23 : 6; 78ba0501acSDingqiang Lin unsigned fmw_dly : 6; 79ba0501acSDingqiang Lin unsigned fmw_dly_en : 1; 80ba0501acSDingqiang Lin unsigned reserved31_31 : 1; 81ba0501acSDingqiang Lin } V6; 8227ffef75SDingqiang Lin struct { 8327ffef75SDingqiang Lin unsigned rwcs : 5; 8427ffef75SDingqiang Lin unsigned rwpw : 6; 8527ffef75SDingqiang Lin unsigned hard_rdy : 1; 8627ffef75SDingqiang Lin unsigned csrw : 6; 8727ffef75SDingqiang Lin unsigned wait_frdy_dly : 5; 8827ffef75SDingqiang Lin unsigned reserved23_23 : 1; 8927ffef75SDingqiang Lin unsigned fmw_dly : 6; 9027ffef75SDingqiang Lin unsigned fmw_dly_en : 1; 9127ffef75SDingqiang Lin unsigned reserved31_31 : 1; 9227ffef75SDingqiang Lin } V9; 93ba0501acSDingqiang Lin }; 94ba0501acSDingqiang Lin 95ba0501acSDingqiang Lin union FL_CTL_T { 96ba0501acSDingqiang Lin u32 d32; 97ba0501acSDingqiang Lin struct { 98ba0501acSDingqiang Lin unsigned rst : 1; 99ba0501acSDingqiang Lin unsigned rdn : 1; 100ba0501acSDingqiang Lin unsigned start : 1; 101ba0501acSDingqiang Lin unsigned dma : 1; 102ba0501acSDingqiang Lin unsigned st_addr : 1; 103ba0501acSDingqiang Lin unsigned tr_count : 2; 104ba0501acSDingqiang Lin unsigned rdy_ignore : 1; 105ba0501acSDingqiang Lin /* unsigned int_clr : 1; */ 106ba0501acSDingqiang Lin /* unsigned int_en : 1; */ 107ba0501acSDingqiang Lin unsigned reserved8_9 : 2; 108ba0501acSDingqiang Lin unsigned cor_en : 1; 109ba0501acSDingqiang Lin unsigned lba_en : 1; 110ba0501acSDingqiang Lin unsigned spare_size : 7; 111ba0501acSDingqiang Lin unsigned reserved19 : 1; 112ba0501acSDingqiang Lin unsigned tr_rdy : 1; 113ba0501acSDingqiang Lin unsigned page_size : 1; 114ba0501acSDingqiang Lin unsigned page_num : 6; 115ba0501acSDingqiang Lin unsigned low_power : 1; 116ba0501acSDingqiang Lin unsigned async_tog_mix : 1; 117ba0501acSDingqiang Lin unsigned reserved30_31 : 2; 118ba0501acSDingqiang Lin } V6; 11927ffef75SDingqiang Lin struct { 12027ffef75SDingqiang Lin unsigned flash_rst : 1; 12127ffef75SDingqiang Lin unsigned flash_rdn : 1; 12227ffef75SDingqiang Lin unsigned flash_st : 1; 12327ffef75SDingqiang Lin unsigned bypass : 1; 12427ffef75SDingqiang Lin unsigned st_addr : 1; 12527ffef75SDingqiang Lin unsigned tr_count : 2; 12627ffef75SDingqiang Lin unsigned flash_st_mod : 1; 12727ffef75SDingqiang Lin unsigned not_tran_data : 1; 12827ffef75SDingqiang Lin unsigned tran_seed : 1; 12927ffef75SDingqiang Lin unsigned cor_able : 1; 13027ffef75SDingqiang Lin unsigned lba_en : 1; 13127ffef75SDingqiang Lin unsigned lba_spare_sel : 1; 13227ffef75SDingqiang Lin unsigned reserved13_18 : 6; 13327ffef75SDingqiang Lin unsigned bchst_trans : 1; 13427ffef75SDingqiang Lin unsigned tr_rdy : 1; 13527ffef75SDingqiang Lin unsigned page_size : 1; 13627ffef75SDingqiang Lin unsigned page_num : 6; 13727ffef75SDingqiang Lin unsigned low_power : 1; 13827ffef75SDingqiang Lin unsigned async_tog_mix : 1; 13927ffef75SDingqiang Lin unsigned bypass_fifo_mode : 1; 14027ffef75SDingqiang Lin unsigned reserved31_31 : 1; 14127ffef75SDingqiang Lin } V9; 142ba0501acSDingqiang Lin }; 143ba0501acSDingqiang Lin 144ba0501acSDingqiang Lin union BCH_CTL_T { 145ba0501acSDingqiang Lin u32 d32; 146ba0501acSDingqiang Lin struct { 147ba0501acSDingqiang Lin unsigned rst : 1; 148ba0501acSDingqiang Lin unsigned reserved : 1; 149ba0501acSDingqiang Lin unsigned addr_not_care : 1; 150ba0501acSDingqiang Lin unsigned power_down : 1; 151ba0501acSDingqiang Lin unsigned bch_mode : 1; /* 0-16bit/1KB, 1-24bit/1KB */ 152ba0501acSDingqiang Lin unsigned region : 3; 153ba0501acSDingqiang Lin unsigned addr : 8; 154ba0501acSDingqiang Lin unsigned bchpage : 1; 155ba0501acSDingqiang Lin unsigned reserved17 : 1; 156ba0501acSDingqiang Lin unsigned bch_mode1 : 1; 157ba0501acSDingqiang Lin unsigned thres : 8; 158ba0501acSDingqiang Lin unsigned reserved27_31 : 5; 159ba0501acSDingqiang Lin } V6; 16027ffef75SDingqiang Lin struct { 16127ffef75SDingqiang Lin unsigned bchrst : 1; 16227ffef75SDingqiang Lin unsigned wcnt_clear : 1; 16327ffef75SDingqiang Lin unsigned reserved2 : 1; 16427ffef75SDingqiang Lin unsigned bchepd : 1; 16527ffef75SDingqiang Lin unsigned reserved4_15 : 12; 16627ffef75SDingqiang Lin unsigned bchpage : 1; 16727ffef75SDingqiang Lin unsigned bchthre : 8; 16827ffef75SDingqiang Lin unsigned bchmode : 3; 16927ffef75SDingqiang Lin unsigned reserved28_31 : 4; 17027ffef75SDingqiang Lin } V9; 171ba0501acSDingqiang Lin }; 172ba0501acSDingqiang Lin 173ba0501acSDingqiang Lin union BCH_ST_T { 174ba0501acSDingqiang Lin u32 d32; 175ba0501acSDingqiang Lin struct { 176ba0501acSDingqiang Lin unsigned errf0 : 1; 177ba0501acSDingqiang Lin unsigned done0 : 1; 178ba0501acSDingqiang Lin unsigned fail0 : 1; 179ba0501acSDingqiang Lin unsigned err_bits0 : 5; 180ba0501acSDingqiang Lin unsigned err_bits_low0 : 5; 181ba0501acSDingqiang Lin unsigned errf1 : 1; 182ba0501acSDingqiang Lin unsigned done1 : 1; 183ba0501acSDingqiang Lin unsigned fail1 : 1; 184ba0501acSDingqiang Lin unsigned err_bits1 : 5; 185ba0501acSDingqiang Lin unsigned err_bits_low1 : 5; 186ba0501acSDingqiang Lin unsigned rdy : 1; 187ba0501acSDingqiang Lin /* unsigned cnt : 1; */ 188ba0501acSDingqiang Lin unsigned err_bits0_5 : 1; 189ba0501acSDingqiang Lin unsigned err_bits_low0_5 : 1; 190ba0501acSDingqiang Lin unsigned err_bits1_5 : 1; 191ba0501acSDingqiang Lin unsigned err_bits_low1_5 : 1; 192ba0501acSDingqiang Lin unsigned reserved31_31 : 1; 193ba0501acSDingqiang Lin } V6; 19427ffef75SDingqiang Lin struct { 19527ffef75SDingqiang Lin unsigned errf0 : 1; 19627ffef75SDingqiang Lin unsigned done0 : 1; 19727ffef75SDingqiang Lin unsigned fail0 : 1; 19827ffef75SDingqiang Lin unsigned err_bits0 : 7; 19927ffef75SDingqiang Lin unsigned all_f_flag0 : 1; 20027ffef75SDingqiang Lin unsigned reserved11_15 : 5; 20127ffef75SDingqiang Lin unsigned errf1 : 1; 20227ffef75SDingqiang Lin unsigned done1 : 1; 20327ffef75SDingqiang Lin unsigned fail1 : 1; 20427ffef75SDingqiang Lin unsigned err_bits1 : 7; 20527ffef75SDingqiang Lin unsigned all_f_flag1 : 1; 20627ffef75SDingqiang Lin unsigned reserved27_30 : 4; 20727ffef75SDingqiang Lin unsigned bch_ready_flag: 1; 20827ffef75SDingqiang Lin } V9; 209ba0501acSDingqiang Lin }; 210ba0501acSDingqiang Lin 211ba0501acSDingqiang Lin union MTRANS_CFG_T { 212ba0501acSDingqiang Lin u32 d32; 213ba0501acSDingqiang Lin struct { 214ba0501acSDingqiang Lin unsigned ahb_wr_st : 1; 215ba0501acSDingqiang Lin unsigned ahb_wr : 1; 216ba0501acSDingqiang Lin unsigned bus_mode : 1; 217ba0501acSDingqiang Lin unsigned hsize : 3; 218ba0501acSDingqiang Lin unsigned burst : 3; 219ba0501acSDingqiang Lin unsigned incr_num : 5; 220ba0501acSDingqiang Lin unsigned fl_pwd : 1; 221ba0501acSDingqiang Lin unsigned ahb_rst : 1; 222ba0501acSDingqiang Lin unsigned reserved16_31 : 16; 223ba0501acSDingqiang Lin } V6; 22427ffef75SDingqiang Lin struct { 22527ffef75SDingqiang Lin unsigned ahb_wr_st : 1; 22627ffef75SDingqiang Lin unsigned ahb_wr : 1; 22727ffef75SDingqiang Lin unsigned bus_mode : 1; 22827ffef75SDingqiang Lin unsigned hsize : 3; 22927ffef75SDingqiang Lin unsigned burst : 3; 23027ffef75SDingqiang Lin unsigned incr_num : 5; 23127ffef75SDingqiang Lin unsigned fl_pwd : 1; 23227ffef75SDingqiang Lin unsigned ahb_rst : 1; 23327ffef75SDingqiang Lin unsigned redundance_size : 11; 23427ffef75SDingqiang Lin unsigned reserved27_31 : 5; 23527ffef75SDingqiang Lin } V9; 236ba0501acSDingqiang Lin }; 237ba0501acSDingqiang Lin 238ba0501acSDingqiang Lin union MTRANS_STAT_T { 239ba0501acSDingqiang Lin u32 d32; 240ba0501acSDingqiang Lin struct { 241ba0501acSDingqiang Lin unsigned bus_err : 16; 242ba0501acSDingqiang Lin unsigned mtrans_cnt : 5; 243ba0501acSDingqiang Lin unsigned reserved21_31 : 11; 244ba0501acSDingqiang Lin } V6; 24527ffef75SDingqiang Lin struct { 24627ffef75SDingqiang Lin unsigned bus_err : 16; 24727ffef75SDingqiang Lin unsigned mtrans_cnt : 6; 24827ffef75SDingqiang Lin unsigned reserved22_31 : 10; 24927ffef75SDingqiang Lin } V9; 250ba0501acSDingqiang Lin }; 251ba0501acSDingqiang Lin 252ba0501acSDingqiang Lin /* NANDC Registers */ 253ba0501acSDingqiang Lin #define NANDC_FMCTL 0x0 254ba0501acSDingqiang Lin #define NANDC_FMWAIT 0x4 255ba0501acSDingqiang Lin #define NANDC_FLCTL 0x8 256ba0501acSDingqiang Lin #define NANDC_BCHCTL 0xc 257ba0501acSDingqiang Lin #define NANDC_MTRANS_CFG 0x10 258ba0501acSDingqiang Lin #define NANDC_MTRANS_SADDR0 0x14 259ba0501acSDingqiang Lin #define NANDC_MTRANS_SADDR1 0x18 260ba0501acSDingqiang Lin #define NANDC_MTRANS_STAT 0x1c 261ba0501acSDingqiang Lin #define NANDC_DLL_CTL_REG0 0x130 262ba0501acSDingqiang Lin #define NANDC_DLL_CTL_REG1 0x134 263ba0501acSDingqiang Lin #define NANDC_DLL_OBS_REG0 0x138 264ba0501acSDingqiang Lin #define NANDC_RANDMZ_CFG 0x150 265ba0501acSDingqiang Lin #define NANDC_EBI_EN 0x154 266ba0501acSDingqiang Lin #define NANDC_FMWAIT_SYN 0x158 267ba0501acSDingqiang Lin #define NANDC_MTRANS_STAT2 0x15c 268ba0501acSDingqiang Lin #define NANDC_NANDC_VER 0x160 269ba0501acSDingqiang Lin #define NANDC_LLP_CTL 0x164 270ba0501acSDingqiang Lin #define NANDC_LLP_STAT 0x168 271ba0501acSDingqiang Lin #define NANDC_INTEN 0x16c 272ba0501acSDingqiang Lin #define NANDC_INTCLR 0x170 273ba0501acSDingqiang Lin #define NANDC_INTST 0x174 274ba0501acSDingqiang Lin #define NANDC_SPARE0 0x200 275ba0501acSDingqiang Lin #define NANDC_SPARE1 0x230 276ba0501acSDingqiang Lin 277ba0501acSDingqiang Lin #define NANDC_BCHST(i) ({ \ 278ba0501acSDingqiang Lin u32 x = (i); \ 279ba0501acSDingqiang Lin 4 * x + x < 8 ? 0x20 : 0x520; }) 280ba0501acSDingqiang Lin 281ba0501acSDingqiang Lin #define NANDC_CHIP_DATA(id) (0x800 + (id) * 0x100) 282ba0501acSDingqiang Lin #define NANDC_CHIP_ADDR(id) (0x800 + (id) * 0x100 + 0x4) 283ba0501acSDingqiang Lin #define NANDC_CHIP_CMD(id) (0x800 + (id) * 0x100 + 0x8) 284ba0501acSDingqiang Lin 28527ffef75SDingqiang Lin #define NANDC_V9_FMCTL 0x0 28627ffef75SDingqiang Lin #define NANDC_V9_FMWAIT 0x4 28727ffef75SDingqiang Lin #define NANDC_V9_FLCTL 0x10 28827ffef75SDingqiang Lin #define NANDC_V9_BCHCTL 0x20 28927ffef75SDingqiang Lin #define NANDC_V9_MTRANS_CFG 0x30 29027ffef75SDingqiang Lin #define NANDC_V9_MTRANS_SADDR0 0x34 29127ffef75SDingqiang Lin #define NANDC_V9_MTRANS_SADDR1 0x38 29227ffef75SDingqiang Lin #define NANDC_V9_MTRANS_STAT 0x40 29327ffef75SDingqiang Lin #define NANDC_V9_MTRANS_STAT2 0x44 29427ffef75SDingqiang Lin #define NANDC_V9_NANDC_VER 0x80 29527ffef75SDingqiang Lin 29627ffef75SDingqiang Lin #define NANDC_V9_INTEN 0x120 29727ffef75SDingqiang Lin #define NANDC_V9_INTCLR 0x124 29827ffef75SDingqiang Lin #define NANDC_V9_INTST 0x128 29927ffef75SDingqiang Lin #define NANDC_V9_SPARE0 0x200 30027ffef75SDingqiang Lin #define NANDC_V9_SPARE1 0x204 30127ffef75SDingqiang Lin #define NANDC_V9_RANDMZ_CFG 0x208 30227ffef75SDingqiang Lin #define NANDC_V9_BCHST(i) (0x150 + (i) * 4) 30327ffef75SDingqiang Lin 30427ffef75SDingqiang Lin #define NANDC_V9_CHIP_DATA(id) (0x800 + (id) * 0x100) 30527ffef75SDingqiang Lin #define NANDC_V9_CHIP_ADDR(id) (0x800 + (id) * 0x100 + 0x4) 30627ffef75SDingqiang Lin #define NANDC_V9_CHIP_CMD(id) (0x800 + (id) * 0x100 + 0x8) 30727ffef75SDingqiang Lin 308ba0501acSDingqiang Lin struct MASTER_INFO_T { 309ba0501acSDingqiang Lin u32 *page_buf; /* [DATA_LEN]; */ 310ba0501acSDingqiang Lin u32 *spare_buf; /* [DATA_LEN / (1024/128)]; */ 311ba0501acSDingqiang Lin u32 *page_vir; /* page_buf_vir_addr */ 312ba0501acSDingqiang Lin u32 *spare_vir; /* spare_buf_vir_addr */ 313ba0501acSDingqiang Lin u32 page_phy; /* page_buf_phy_addr */ 314ba0501acSDingqiang Lin u32 spare_phy; /* spare_buf_phy_addr*/ 315ba0501acSDingqiang Lin u32 mapped; 316ba0501acSDingqiang Lin u32 cnt; 317ba0501acSDingqiang Lin }; 318ba0501acSDingqiang Lin 319ba0501acSDingqiang Lin struct CHIP_MAP_INFO_T { 320ba0501acSDingqiang Lin u32 *nandc_addr; 321ba0501acSDingqiang Lin u32 chip_num; 322ba0501acSDingqiang Lin }; 323ba0501acSDingqiang Lin 324ba0501acSDingqiang Lin unsigned long rknandc_dma_map_single(unsigned long ptr, 325ba0501acSDingqiang Lin int size, 326ba0501acSDingqiang Lin int dir); 327ba0501acSDingqiang Lin void rknandc_dma_unmap_single(unsigned long ptr, 328ba0501acSDingqiang Lin int size, 329ba0501acSDingqiang Lin int dir); 330ba0501acSDingqiang Lin 331ba0501acSDingqiang Lin void nandc_init(void __iomem *nandc_addr); 332ba0501acSDingqiang Lin void nandc_flash_cs(u8 chip_sel); 333ba0501acSDingqiang Lin void nandc_flash_de_cs(u8 chip_sel); 334ba0501acSDingqiang Lin u32 nandc_wait_flash_ready(u8 chip_sel); 335ba0501acSDingqiang Lin u32 nandc_delayns(u32 count); 336ba0501acSDingqiang Lin u32 nandc_xfer_data(u8 chip_sel, 337ba0501acSDingqiang Lin u8 dir, 338ba0501acSDingqiang Lin u8 sector_count, 339ba0501acSDingqiang Lin u32 *p_data, 340ba0501acSDingqiang Lin u32 *p_spare); 341ba0501acSDingqiang Lin void nandc_randmz_sel(u8 chip_sel, u32 randmz_seed); 342ba0501acSDingqiang Lin void nandc_bch_sel(u8 bits); 343ba0501acSDingqiang Lin void nandc_read_not_case_busy_en(u8 en); 344ba0501acSDingqiang Lin void nandc_time_cfg(u32 ns); 345ba0501acSDingqiang Lin void nandc_clean_irq(void); 346*57d18453Sjon.lin u8 nandc_get_version(void); 347ba0501acSDingqiang Lin 348ba0501acSDingqiang Lin #endif 349