1d67b0d97SEric Nelson/* 2d67b0d97SEric Nelson * Copyright (C) 2013 Boundary Devices 3d67b0d97SEric Nelson * 4*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 5d67b0d97SEric Nelson * 6d67b0d97SEric Nelson * Device Configuration Data (DCD) 7d67b0d97SEric Nelson * 8d67b0d97SEric Nelson * Each entry must have the format: 9d67b0d97SEric Nelson * Addr-type Address Value 10d67b0d97SEric Nelson * 11d67b0d97SEric Nelson * where: 12d67b0d97SEric Nelson * Addr-type register length (1,2 or 4 bytes) 13d67b0d97SEric Nelson * Address absolute address of the register 14d67b0d97SEric Nelson * value value to be stored in the register 15d67b0d97SEric Nelson */ 16d67b0d97SEric Nelson 17d67b0d97SEric Nelson/* set the default clock gate to save power */ 18d67b0d97SEric NelsonDATA 4, CCM_CCGR0, 0x00C03F3F 19d67b0d97SEric NelsonDATA 4, CCM_CCGR1, 0x0030FC03 20d67b0d97SEric NelsonDATA 4, CCM_CCGR2, 0x0FFFC000 21d67b0d97SEric NelsonDATA 4, CCM_CCGR3, 0x3FF00000 22d67b0d97SEric NelsonDATA 4, CCM_CCGR4, 0x00FFF300 23d67b0d97SEric NelsonDATA 4, CCM_CCGR5, 0x0F0000C3 24d67b0d97SEric NelsonDATA 4, CCM_CCGR6, 0x000003FF 25d67b0d97SEric Nelson 26d67b0d97SEric Nelson/* enable AXI cache for VDOA/VPU/IPU */ 27d67b0d97SEric NelsonDATA 4, MX6_IOMUXC_GPR4, 0xF00000CF 28d67b0d97SEric Nelson/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 29d67b0d97SEric NelsonDATA 4, MX6_IOMUXC_GPR6, 0x007F007F 30d67b0d97SEric NelsonDATA 4, MX6_IOMUXC_GPR7, 0x007F007F 31492938a3SFabio Estevam 32492938a3SFabio Estevam/* 33492938a3SFabio Estevam * Setup CCM_CCOSR register as follows: 34492938a3SFabio Estevam * 35492938a3SFabio Estevam * cko1_en = 1 --> CKO1 enabled 36492938a3SFabio Estevam * cko1_div = 111 --> divide by 8 37492938a3SFabio Estevam * cko1_sel = 1011 --> ahb_clk_root 38492938a3SFabio Estevam * 39492938a3SFabio Estevam * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz 40492938a3SFabio Estevam */ 41492938a3SFabio EstevamDATA 4, CCM_CCOSR, 0x000000fb 42