1c2cde27dSStefan Roese/* 2c2cde27dSStefan Roese * Projectiondesign AS 3c2cde27dSStefan Roese * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg 4c2cde27dSStefan Roese * 5c2cde27dSStefan Roese * Copyright (C) 2011 Freescale Semiconductor, Inc. 6c2cde27dSStefan Roese * Jason Liu <r64343@freescale.com> 7c2cde27dSStefan Roese * 8c2cde27dSStefan Roese * SPDX-License-Identifier: GPL-2.0+ 9c2cde27dSStefan Roese * 10*03bf9d58SJagan Teki * Refer doc/README.imximage for more details about how-to configure 11c2cde27dSStefan Roese * and create imximage boot image 12c2cde27dSStefan Roese * 13c2cde27dSStefan Roese * The syntax is taken as close as possible with the kwbimage 14c2cde27dSStefan Roese */ 15c2cde27dSStefan Roese 16c2cde27dSStefan Roese/* image version */ 17c2cde27dSStefan Roese 18c2cde27dSStefan RoeseIMAGE_VERSION 2 19c2cde27dSStefan Roese 20c2cde27dSStefan Roese/* 21c2cde27dSStefan Roese * Boot Device : one of 22c2cde27dSStefan Roese * sd, nand 23c2cde27dSStefan Roese */ 24c2cde27dSStefan RoeseBOOT_FROM nand 25c2cde27dSStefan Roese 26c2cde27dSStefan Roese/* 27c2cde27dSStefan Roese * Device Configuration Data (DCD) 28c2cde27dSStefan Roese * 29c2cde27dSStefan Roese * Each entry must have the format: 30c2cde27dSStefan Roese * Addr-type Address Value 31c2cde27dSStefan Roese * 32c2cde27dSStefan Roese * where: 33c2cde27dSStefan Roese * Addr-type register length (1,2 or 4 bytes) 34c2cde27dSStefan Roese * Address absolute address of the register 35c2cde27dSStefan Roese * value value to be stored in the register 36c2cde27dSStefan Roese */ 37c2cde27dSStefan Roese 38c2cde27dSStefan Roese#define __ASSEMBLY__ 39c2cde27dSStefan Roese#include <config.h> 40c2cde27dSStefan Roese#include "asm/arch/mx6-ddr.h" 41c2cde27dSStefan Roese#include "asm/arch/iomux.h" 42c2cde27dSStefan Roese#include "asm/arch/crm_regs.h" 43c2cde27dSStefan Roese 44c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 45c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 46c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 47c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 48c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 49c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 50c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 51c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 52c2cde27dSStefan Roese 53c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 54c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 55c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 56c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 57c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 58c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 59c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 60c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 61c2cde27dSStefan Roese 62c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_CAS, 0x00020030 63c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_RAS, 0x00020030 64c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 65c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 66c2cde27dSStefan Roese 67c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_RESET, 0x00020030 68c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 69c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 70c2cde27dSStefan Roese 71c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 72c2cde27dSStefan Roese 73c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 74c2cde27dSStefan RoeseDATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 75c2cde27dSStefan Roese 76c2cde27dSStefan RoeseDATA 4, MX6_IOM_GRP_B0DS, 0x00000030 77c2cde27dSStefan RoeseDATA 4, MX6_IOM_GRP_B1DS, 0x00000030 78c2cde27dSStefan RoeseDATA 4, MX6_IOM_GRP_B2DS, 0x00000030 79c2cde27dSStefan RoeseDATA 4, MX6_IOM_GRP_B3DS, 0x00000030 80c2cde27dSStefan RoeseDATA 4, MX6_IOM_GRP_B4DS, 0x00000030 81c2cde27dSStefan RoeseDATA 4, MX6_IOM_GRP_B5DS, 0x00000030 82c2cde27dSStefan RoeseDATA 4, MX6_IOM_GRP_B6DS, 0x00000030 83c2cde27dSStefan RoeseDATA 4, MX6_IOM_GRP_B7DS, 0x00000030 84c2cde27dSStefan RoeseDATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 85c2cde27dSStefan Roese 86c2cde27dSStefan Roese/* (differential input) */ 87c2cde27dSStefan RoeseDATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 88c2cde27dSStefan Roese/* disable ddr pullups */ 89c2cde27dSStefan RoeseDATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 90c2cde27dSStefan Roese/* (differential input) */ 91c2cde27dSStefan RoeseDATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 92c2cde27dSStefan Roese/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 93c2cde27dSStefan RoeseDATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 94c2cde27dSStefan Roese/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 95c2cde27dSStefan RoeseDATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 96c2cde27dSStefan Roese 97c2cde27dSStefan Roese/* Read data DQ Byte0-3 delay */ 98c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 99c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 100c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 101c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 102c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 103c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 104c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 105c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 106c2cde27dSStefan Roese 107c2cde27dSStefan Roese/* 108c2cde27dSStefan Roese * MDMISC mirroring interleaved (row/bank/col) 109c2cde27dSStefan Roese */ 110c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 111c2cde27dSStefan Roese 112c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 113c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975 114c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64 115c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB 116c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 117c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21 118c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 119c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 120c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDASP, 0x00000017 121c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 122c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 123c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A 124c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 125c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B 126c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 127c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDSCR, 0x00428039 128c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 129c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 130c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 131c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 132c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 133c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 134c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDREF, 0x00005800 135c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 136c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 137c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350 138c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359 139c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350 140c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348 141c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B 142c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341 143c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933 144c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36 145c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F 146c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F 147c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044 148c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044 149c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 150c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 151c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 152c2cde27dSStefan RoeseDATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 153c2cde27dSStefan Roese 154c2cde27dSStefan Roese/* set the default clock gate to save power */ 155c2cde27dSStefan RoeseDATA 4, CCM_CCGR0, 0x00C03F3F 156c2cde27dSStefan RoeseDATA 4, CCM_CCGR1, 0x0030FC03 157c2cde27dSStefan RoeseDATA 4, CCM_CCGR2, 0x0FFFC000 158c2cde27dSStefan RoeseDATA 4, CCM_CCGR3, 0x3FF00000 159c2cde27dSStefan RoeseDATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ 160c2cde27dSStefan RoeseDATA 4, CCM_CCGR5, 0x0F0000C3 161c2cde27dSStefan RoeseDATA 4, CCM_CCGR6, 0x000003FF 162c2cde27dSStefan Roese 163c2cde27dSStefan Roese/* enable AXI cache for VDOA/VPU/IPU */ 164c2cde27dSStefan RoeseDATA 4, MX6_IOMUXC_GPR4, 0xF00000CF 165c2cde27dSStefan Roese/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 166c2cde27dSStefan RoeseDATA 4, MX6_IOMUXC_GPR6, 0x007F007F 167c2cde27dSStefan RoeseDATA 4, MX6_IOMUXC_GPR7, 0x007F007F 168