| /rk3399_rockchip-uboot/drivers/video/drm/rk628/ |
| H A D | rk628_combtxphy.c | 200 void rk628_combtxphy_set_bus_width(struct rk628 *rk628, u32 bus_width) in rk628_combtxphy_set_bus_width() argument
202 rk628->combtxphy.bus_width = bus_width; in rk628_combtxphy_set_bus_width()
207 return rk628->combtxphy.bus_width; in rk628_combtxphy_get_bus_width()
223 int bus_width = rk628_combtxphy_get_bus_width(rk628); in rk628_combtxphy_set_mode() local
224 unsigned int fhsc = bus_width >> 8; in rk628_combtxphy_set_mode()
225 unsigned int flags = bus_width & 0xff; in rk628_combtxphy_set_mode()
266 combtxphy->bus_width = fhsc; in rk628_combtxphy_set_mode()
272 int bus_width = rk628_combtxphy_get_bus_width(rk628); in rk628_combtxphy_set_mode() local
273 unsigned int flags = bus_width & 0xff; in rk628_combtxphy_set_mode()
274 unsigned int rate = (bus_width >> 8) * 7; in rk628_combtxphy_set_mode()
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| H A D | rk628_lvds.c | 66 u32 val, mask, bus_width; in rk628_lvds_enable() local
82 bus_width = COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN; in rk628_lvds_enable()
87 bus_width = COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN; in rk628_lvds_enable()
94 bus_width = COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN; in rk628_lvds_enable()
101 bus_width = COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN; in rk628_lvds_enable()
107 bus_width = COMBTXPHY_MODULEA_EN; in rk628_lvds_enable()
115 bus_width |= (mode->clock / 1000) << 8; in rk628_lvds_enable()
116 rk628_combtxphy_set_bus_width(rk628, bus_width); in rk628_lvds_enable()
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| /rk3399_rockchip-uboot/drivers/mmc/ |
| H A D | s5p_sdhci.c | 98 if (host->bus_width == 8) in s5p_sdhci_core_init()
108 int s5p_sdhci_init(u32 regbase, int index, int bus_width) in s5p_sdhci_init() argument
117 host->bus_width = bus_width; in s5p_sdhci_init()
129 flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; in do_sdhci_init()
160 int bus_width, dev_id; in sdhci_get_config() local
172 bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); in sdhci_get_config()
173 if (bus_width <= 0) { in sdhci_get_config()
177 host->bus_width = bus_width; in sdhci_get_config()
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| H A D | hi6220_dw_mmc.c | 41 int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width) in hi6220_dwmci_add_port() argument
52 host->buswidth = bus_width; in hi6220_dwmci_add_port()
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| H A D | fsl_esdhc.c | 108 unsigned int bus_width; member
619 if (mmc->bus_width == 4) in esdhc_set_ios_common()
621 else if (mmc->bus_width == 8) in esdhc_set_ios_common()
836 if (priv->bus_width == 8) in fsl_esdhc_init()
838 else if (priv->bus_width == 4) in fsl_esdhc_init()
846 if (priv->bus_width > 0) { in fsl_esdhc_init()
847 if (priv->bus_width < 8) in fsl_esdhc_init()
849 if (priv->bus_width < 4) in fsl_esdhc_init()
877 priv->bus_width = cfg->max_bus_width; in fsl_esdhc_cfg_to_priv()
1041 priv->bus_width = 8; in fsl_esdhc_probe()
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| H A D | sunxi_mmc.c | 238 mmc->bus_width, mmc->clock); in sunxi_mmc_set_ios_common()
247 if (mmc->bus_width == 8) in sunxi_mmc_set_ios_common()
249 else if (mmc->bus_width == 4) in sunxi_mmc_set_ios_common()
567 int bus_width, ret; in sunxi_mmc_probe() local
570 bus_width = dev_read_u32_default(dev, "bus-width", 1); in sunxi_mmc_probe()
574 if (bus_width == 8) in sunxi_mmc_probe()
576 if (bus_width >= 4) in sunxi_mmc_probe()
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| H A D | tegra_mmc.c | 421 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); in tegra_mmc_set_ios()
436 if (mmc->bus_width == 8) in tegra_mmc_set_ios()
438 else if (mmc->bus_width == 4) in tegra_mmc_set_ios()
598 int bus_width, ret; in tegra_mmc_probe() local
602 bus_width = dev_read_u32_default(dev, "bus-width", 1); in tegra_mmc_probe()
606 if (bus_width == 8) in tegra_mmc_probe()
608 if (bus_width >= 4) in tegra_mmc_probe()
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| H A D | sh_mmcif.c | 361 switch (host->bus_width) { in sh_mmcif_set_cmd()
549 if (mmc->bus_width == 8) in sh_mmcif_set_ios()
550 host->bus_width = MMC_BUS_WIDTH_8; in sh_mmcif_set_ios()
551 else if (mmc->bus_width == 4) in sh_mmcif_set_ios()
552 host->bus_width = MMC_BUS_WIDTH_4; in sh_mmcif_set_ios()
554 host->bus_width = MMC_BUS_WIDTH_1; in sh_mmcif_set_ios()
556 debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width); in sh_mmcif_set_ios()
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| /rk3399_rockchip-uboot/arch/arm/mach-s5pc1xx/include/mach/ |
| H A D | mmc.h | 56 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
58 static inline int s5p_mmc_init(int index, int bus_width) in s5p_mmc_init() argument
63 return s5p_sdhci_init(base, index, bus_width); in s5p_mmc_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-exynos/include/mach/ |
| H A D | mmc.h | 58 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
60 static inline int s5p_mmc_init(int index, int bus_width) in s5p_mmc_init() argument
65 return s5p_sdhci_init(base, index, bus_width); in s5p_mmc_init()
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| /rk3399_rockchip-uboot/drivers/video/ |
| H A D | mxsfb.c | 54 uint32_t word_len = 0, bus_width = 0; in mxs_lcd_init() local
66 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT; in mxs_lcd_init()
71 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT; in mxs_lcd_init()
76 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT; in mxs_lcd_init()
81 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT; in mxs_lcd_init()
86 writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE | in mxs_lcd_init()
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| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | rockchip_phy.h | 24 int (*set_bus_width)(struct rockchip_phy *phy, u32 bus_width);
41 int rockchip_phy_set_bus_width(struct rockchip_phy *phy, u32 bus_width);
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| H A D | rockchip_phy.c | 55 int rockchip_phy_set_bus_width(struct rockchip_phy *phy, u32 bus_width) in rockchip_phy_set_bus_width() argument
61 return phy->funcs->set_bus_width(phy, bus_width); in rockchip_phy_set_bus_width()
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| H A D | inno_video_phy.c | 187 inno_video_phy_set_bus_width(struct rockchip_phy *phy, u32 bus_width) in inno_video_phy_set_bus_width() argument
191 inno->dual_channel = (bus_width == 2) ? true : false; in inno_video_phy_set_bus_width()
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| /rk3399_rockchip-uboot/drivers/ddr/fsl/ |
| H A D | ddr3_dimm_params.c | 64 if ((spd->bus_width & 0x7) < 4) in compute_ranksize()
65 nbit_primary_bus_width = (spd->bus_width & 0x7) + 3; in compute_ranksize()
123 pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7)); in ddr_compute_dimm_parameters()
124 if ((spd->bus_width >> 3) & 0x3) in ddr_compute_dimm_parameters()
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| H A D | ddr4_dimm_params.c | 96 if ((spd->bus_width & 0x7) < 4) in compute_ranksize()
97 nbit_primary_bus_width = (spd->bus_width & 0x7) + 3; in compute_ranksize()
166 pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7)); in ddr_compute_dimm_parameters()
167 if ((spd->bus_width >> 3) & 0x3) in ddr_compute_dimm_parameters()
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| H A D | arm_ddr_gen3.c | 34 unsigned int i, bus_width; in fsl_ddr_set_memctl_regs() local
223 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) in fsl_ddr_set_memctl_regs()
225 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / in fsl_ddr_set_memctl_regs()
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| /rk3399_rockchip-uboot/arch/arm/mach-sunxi/ |
| H A D | dram_sun6i.c | 23 u8 bus_width; member
65 if (para->bus_width == 32) { in mctl_dll_init()
75 if (para->bus_width == 32) { in mctl_dll_init()
85 if (para->bus_width == 32) { in mctl_dll_init()
183 para->bus_width = 16; in mctl_channel_init()
244 if (para->bus_width == 16) in mctl_channel_init()
273 ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) | in mctl_com_init()
338 .bus_width = 32, in sunxi_dram_init()
384 bus = (para.bus_width == 32) ? 2 : 1; in sunxi_dram_init()
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| H A D | dram_sun8i_a33.c | 29 u8 bus_width; member
41 ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | in mctl_set_cr()
234 para->bus_width = 16; in mctl_channel_init()
277 para->bus_width = 8; in mctl_channel_init()
340 .bus_width = 16, in sunxi_dram_init()
360 return para.page_size * (para.bus_width / 8) * in sunxi_dram_init()
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| H A D | dram_sun8i_a23.c | 91 static void mctl_init(u32 *bus_width) in mctl_init() argument
245 *bus_width = 8; in mctl_init()
252 *bus_width = 16; in mctl_init()
272 u32 bus, bus_width, offset, page_size, rows; in sunxi_dram_init() local
275 mctl_init(&bus_width); in sunxi_dram_init()
277 if (bus_width == 16) { in sunxi_dram_init()
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| H A D | dram_sun8i_a83t.c | 27 u8 bus_width; member
40 ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | in mctl_set_cr()
317 para->bus_width = 16; in mctl_channel_init()
369 para->bus_width = 8; in mctl_channel_init()
417 para->bus_width = 16; in mctl_sys_init()
438 .bus_width = 16, in sunxi_dram_init()
470 return para.page_size * (para.bus_width / 8) * in sunxi_dram_init()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-hi6220/ |
| H A D | dwmmc.h | 8 int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width);
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-hi3798cv200/ |
| H A D | dwmmc.h | 11 int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width);
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| /rk3399_rockchip-uboot/board/sunxi/ |
| H A D | dram_sun4i_auto.c | 10 .bus_width = 0,
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| H A D | dram_sun5i_auto.c | 13 .bus_width = 0,
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