156333be9SHans de Goede /* DRAM parameters for auto dram configuration on sun5i and sun7i */
26c46c8e8SHans de Goede
36c46c8e8SHans de Goede #include <common.h>
46c46c8e8SHans de Goede #include <asm/arch/dram.h>
56c46c8e8SHans de Goede
66c46c8e8SHans de Goede static struct dram_para dram_para = {
76c46c8e8SHans de Goede .clock = CONFIG_DRAM_CLK,
847e3501aSSiarhei Siamashka .mbus_clock = CONFIG_DRAM_MBUS_CLK,
96c46c8e8SHans de Goede .type = 3,
106c46c8e8SHans de Goede .rank_num = 1,
116c46c8e8SHans de Goede .density = 0,
126c46c8e8SHans de Goede .io_width = 0,
136c46c8e8SHans de Goede .bus_width = 0,
146c46c8e8SHans de Goede .zq = CONFIG_DRAM_ZQ,
15*8975cdf4SHans de Goede .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN),
166c46c8e8SHans de Goede .size = 0,
17d133647aSSiarhei Siamashka #ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC
18d133647aSSiarhei Siamashka .cas = 9,
196c46c8e8SHans de Goede .tpr0 = 0x42d899b7,
206c46c8e8SHans de Goede .tpr1 = 0xa090,
216c46c8e8SHans de Goede .tpr2 = 0x22a00,
22d133647aSSiarhei Siamashka .emr2 = 0x10,
23d133647aSSiarhei Siamashka #else
24d133647aSSiarhei Siamashka # include "dram_timings_sun4i.h"
2547e3501aSSiarhei Siamashka .active_windowing = 1,
26d133647aSSiarhei Siamashka #endif
278d6e18dfSAdam Sampson .tpr3 = CONFIG_DRAM_TPR3,
286c46c8e8SHans de Goede .tpr4 = 0,
296c46c8e8SHans de Goede .tpr5 = 0,
306c46c8e8SHans de Goede .emr1 = CONFIG_DRAM_EMR1,
316c46c8e8SHans de Goede .emr3 = 0,
3247e3501aSSiarhei Siamashka .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY,
336c46c8e8SHans de Goede };
346c46c8e8SHans de Goede
sunxi_dram_init(void)356c46c8e8SHans de Goede unsigned long sunxi_dram_init(void)
366c46c8e8SHans de Goede {
376c46c8e8SHans de Goede return dramc_init(&dram_para);
386c46c8e8SHans de Goede }
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