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9e3ffb10 |
| 24-Dec-2021 |
Guochun Huang <hero.huang@rock-chips.com> |
Revert "video/drm: rockchip_phy: simplify PHY mode type"
This reverts commit 5a7ad828056a52df2c7e539d5c2fca9e9d45b8b1.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Ibda62f6d8
Revert "video/drm: rockchip_phy: simplify PHY mode type"
This reverts commit 5a7ad828056a52df2c7e539d5c2fca9e9d45b8b1.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Ibda62f6d8b9a5ff172fca92cc267b367d24ba978
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9fb0493f |
| 10-Dec-2018 |
Wyon Bi <bivvy.bi@rock-chips.com> |
phy/rockchip: Add support for INNOSILICON LVDS/TTL PHY
Innosilicon LVDS/TTL PHY implements LVDS TIA/EIA protocol.
Normally, Innosilicon LVDS/TTL PHY contains four 7-bit
parallel-load serial-out shif
phy/rockchip: Add support for INNOSILICON LVDS/TTL PHY
Innosilicon LVDS/TTL PHY implements LVDS TIA/EIA protocol.
Normally, Innosilicon LVDS/TTL PHY contains four 7-bit
parallel-load serial-out shift registers, a 7X clock PLL,
and five Low-Voltage Differential Signaling (LVDS) line drivers
in a single integrated circuit. These functions allow 28 bits
of single-ended LVTTL data to be synchronously transmitted over
five balanced-pair conductors for receipt by a compatible receiver.
In addition, Innosilicon LVDS/TTL PHY could extend from 4 lanes
to N lanes (N is required by the customer). Therefore, the TTL
lines extend respectively.
Change-Id: I2b6b9cccd88c8ca89ef5f45e964e9eb936777ffc
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
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