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Searched refs:__raw_readl (Results 1 – 25 of 83) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/mach-keystone/
H A Dpsc.c54 ptstat = __raw_readl(KS2_PSC_BASE + PSC_REG_PSTAT); in psc_wait()
74 domain_num = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); in psc_get_domain_num()
107 v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); in psc_set_state()
124 pdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num)); in psc_set_state()
131 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_state()
137 ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD); in psc_set_state()
161 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_enable_module()
179 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_disable_module()
205 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_reset_iso()
209 v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); in psc_set_reset_iso()
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H A Dcmd_ddr3.c45 value = __raw_readl(index); in ddr_memory_test()
48 index, value, __raw_readl(index)); in ddr_memory_test()
71 value = __raw_readl(index); in ddr_memory_test()
74 index, value, __raw_readl(index)); in ddr_memory_test()
142 value = __raw_readl(index); in ddr_memory_compare()
143 value2 = __raw_readl(index2); in ddr_memory_compare()
164 value1 = __raw_readl(address); in ddr_memory_ecc_err()
168 value3 = __raw_readl(address); in ddr_memory_ecc_err()
178 value1 = __raw_readl(address); in ddr_memory_ecc_err()
H A Dddr3.c29 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) in ddr3_init_ddrphy()
35 tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET); in ddr3_init_ddrphy()
45 tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET); in ddr3_init_ddrphy()
64 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) in ddr3_init_ddrphy()
98 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) in ddr3_init_ddrphy()
115 u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET); in ddr3_ecc_support_rmw()
134 data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); in ddr3_ecc_config()
332 u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET); in ddr3_check_ecc_int()
350 value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); in ddr3_check_ecc_int()
353 value = __raw_readl(base + in ddr3_check_ecc_int()
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/rk3399_rockchip-uboot/drivers/rtc/
H A Dimxdi.c82 if ((__raw_readl(&data.regs->dsr) & DSR_WEF) == 0) in clear_write_error()
109 if ((__raw_readl(&data.regs->dsr) & (DSR_WCF | DSR_WEF)) != 0) { in di_write_wait()
120 if (__raw_readl(&data.regs->dsr) & DSR_WEF) { in di_write_wait()
141 if (__raw_readl(&data.regs->dsr) & DSR_NVF) { in di_init()
156 if (__raw_readl(&data.regs->dsr) & DSR_CAF) { in di_init()
163 if (__raw_readl(&data.regs->dtcmr) == 0) { in di_init()
170 if (!(__raw_readl(&data.regs->dcr) & DCR_TCE)) { in di_init()
171 rc = DI_WRITE_WAIT(__raw_readl(&data.regs->dcr) | DCR_TCE, dcr); in di_init()
194 now = __raw_readl(&data.regs->dtcmr); in rtc_get()
/rk3399_rockchip-uboot/drivers/video/
H A Dipu_common.c154 reg = __raw_readl(clk->enable_reg); in clk_ipu_enable()
160 reg = __raw_readl(&mxc_ccm->ccdr); in clk_ipu_enable()
165 reg = __raw_readl(&mxc_ccm->clpcr); in clk_ipu_enable()
176 reg = __raw_readl(clk->enable_reg); in clk_ipu_disable()
185 reg = __raw_readl(&mxc_ccm->ccdr); in clk_ipu_disable()
190 reg = __raw_readl(&mxc_ccm->clpcr); in clk_ipu_disable()
275 #define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma))
282 div = __raw_readl(DI_BS_CLKGEN0(clk->id)); in ipu_pixel_clk_recalc()
364 u32 disp_gen = __raw_readl(IPU_DISP_GEN); in ipu_pixel_clk_enable()
373 u32 disp_gen = __raw_readl(IPU_DISP_GEN); in ipu_pixel_clk_disable()
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H A Dipu_disp.c141 u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1); in ipu_dmfc_set_wait4eot()
195 reg = __raw_readl(DI_DW_GEN(di, wave_gen)); in ipu_di_data_pin_config()
232 reg = __raw_readl(DI_STP_REP(di, wave_gen)); in ipu_di_sync_config()
243 reg = __raw_readl(DC_MAP_CONF_VAL(ptr)); in ipu_dc_map_config()
248 reg = __raw_readl(DC_MAP_CONF_PTR(map)); in ipu_dc_map_config()
256 u32 reg = __raw_readl(DC_MAP_CONF_PTR(map)); in ipu_dc_map_clear()
284 reg = __raw_readl(DC_RL_CH(chan, event)); in ipu_dc_link_event()
387 reg = __raw_readl(DP_COM_CONF()); in ipu_dp_csc_setup()
413 reg = __raw_readl(IPU_SRM_PRI2) | 0x8; in ipu_dp_csc_setup()
469 reg = __raw_readl(DP_COM_CONF()); in ipu_dp_init()
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/rk3399_rockchip-uboot/post/cpu/mpc83xx/
H A Decc.c63 if (__raw_readl(&ddr->err_disable) & ECC_ERROR_ENABLE) { in ecc_post_test()
111 if (!(__raw_readl(&ddr->err_detect) & ECC_ERROR_DETECT_SBE) || in ecc_post_test()
112 (__raw_readl(&ddr->data_err_inject_hi) != in ecc_post_test()
113 (__raw_readl(&ddr->capture_data_hi) ^ pattern[0])) || in ecc_post_test()
114 (__raw_readl(&ddr->data_err_inject_lo) != in ecc_post_test()
115 (__raw_readl(&ddr->capture_data_lo) ^ pattern[1]))) { in ecc_post_test()
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx6/
H A Dclock.c32 reg = __raw_readl(&imx_ccm->CCGR2); in enable_ocotp_clk()
86 reg = __raw_readl(&imx_ccm->CCGR6); in enable_usboh3_clk()
167 reg = __raw_readl(&imx_ccm->CCGR2); in enable_i2c_clk()
183 reg = __raw_readl(addr); in enable_i2c_clk()
204 reg = __raw_readl(&imx_ccm->CCGR1); in enable_spi_clk()
218 div = __raw_readl(&imx_ccm->analog_pll_sys); in decode_pll()
223 div = __raw_readl(&imx_ccm->analog_pll_528); in decode_pll()
228 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl); in decode_pll()
233 div = __raw_readl(&imx_ccm->analog_pll_enet); in decode_pll()
238 div = __raw_readl(&imx_ccm->analog_pll_audio); in decode_pll()
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/rk3399_rockchip-uboot/drivers/mtd/nand/raw/
H A Ddavinci_nand.c81 *(u32 *)buf = __raw_readl(nand); in nand_davinci_read_buf()
170 ecc = __raw_readl(&(davinci_emif_regs->nandfecc[ in nand_davinci_readecc()
183 val = __raw_readl(&davinci_emif_regs->nandfcr); in nand_davinci_enable_hwecc()
485 val = __raw_readl(&davinci_emif_regs->nandfcr); in nand_davinci_4bit_enable_hwecc()
493 val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]); in nand_davinci_4bit_enable_hwecc()
505 ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) & in nand_davinci_4bit_readecc()
627 val = __raw_readl(&davinci_emif_regs->nandfsr); in nand_davinci_4bit_correct_data()
643 val = __raw_readl(&davinci_emif_regs->nanderradd1); in nand_davinci_4bit_correct_data()
660 val = __raw_readl(&davinci_emif_regs->nandfsr); in nand_davinci_4bit_correct_data()
671 val = __raw_readl(&davinci_emif_regs->nandfsr); in nand_davinci_4bit_correct_data()
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/rk3399_rockchip-uboot/drivers/net/
H A Dxilinx_emaclite.c158 val = __raw_readl(reg); in wait_for_bit()
197 u32 ctrl_reg = __raw_readl(&regs->mdioctrl); in phyread()
207 *data = __raw_readl(&regs->mdiord); in phyread()
225 u32 ctrl_reg = __raw_readl(&regs->mdioctrl); in phywrite()
342 while ((__raw_readl(&regs->tx_ping_tsr) & in emaclite_start()
353 while ((__raw_readl(&regs->tx_pong_tsr) & in emaclite_start()
368 if (__raw_readl(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK) in emaclite_start()
385 tmp = ~__raw_readl(&regs->tx_ping_tsr); in xemaclite_txbufferavailable()
387 tmp |= ~__raw_readl(&regs->tx_pong_tsr); in xemaclite_txbufferavailable()
419 reg = __raw_readl(&regs->tx_ping_tsr); in emaclite_send()
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/rk3399_rockchip-uboot/cmd/
H A Dtsi148.c92 if ((__raw_readl(&dev->uregs->vstat) & 0x00000100) != 0) in tsi148_init()
113 val = __raw_readl(&dev->uregs->vstat); in tsi148_init()
205 i, ntohl(__raw_readl(&dev->uregs->outbound[i].otat))); in tsi148_pci_slave_window()
207 i, ntohl(__raw_readl(&dev->uregs->outbound[i].otsal))); in tsi148_pci_slave_window()
209 i, ntohl(__raw_readl(&dev->uregs->outbound[i].oteal))); in tsi148_pci_slave_window()
211 i, ntohl(__raw_readl(&dev->uregs->outbound[i].otofl))); in tsi148_pci_slave_window()
298 i, ntohl(__raw_readl(&dev->uregs->inbound[i].itat))); in tsi148_vme_slave_window()
300 i, ntohl(__raw_readl(&dev->uregs->inbound[i].itsal))); in tsi148_vme_slave_window()
302 i, ntohl(__raw_readl(&dev->uregs->inbound[i].iteal))); in tsi148_vme_slave_window()
304 i, ntohl(__raw_readl(&dev->uregs->inbound[i].itofl))); in tsi148_vme_slave_window()
/rk3399_rockchip-uboot/drivers/serial/
H A Dserial_linflexuart.c64 if (!(__raw_readl(&base->uartsr) & UARTSR_RMB)) in _linflex_serial_getc()
67 c = __raw_readl(&base->bdrm); in _linflex_serial_getc()
103 while ((__raw_readl(&base->linsr) & LINSR_LINS_MASK) != in _linflex_serial_init()
116 ctrl = __raw_readl(&base->lincr1); in _linflex_serial_init()
159 uint32_t uartsr = __raw_readl(&priv->lfuart->uartsr); in linflex_serial_pending()
/rk3399_rockchip-uboot/drivers/usb/host/
H A Dehci-mx5.c94 v = __raw_readl(usbother_base + in mxc_set_usbcontrol()
115 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); in mxc_set_usbcontrol()
135 v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET); in mxc_set_usbcontrol()
140 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); in mxc_set_usbcontrol()
155 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); in mxc_set_usbcontrol()
168 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); in mxc_set_usbcontrol()
193 v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET); in mxc_set_usbcontrol()
/rk3399_rockchip-uboot/drivers/dma/
H A Dti-edma3.c96 opt = __raw_readl(&rg->opt); in edma3_set_dest()
127 src_dst_bidx = __raw_readl(&rg->src_dst_bidx); in edma3_set_dest_index()
128 src_dst_cidx = __raw_readl(&rg->src_dst_cidx); in edma3_set_dest_index()
167 opt = __raw_readl(&rg->opt); in edma3_set_src()
198 src_dst_bidx = __raw_readl(&rg->src_dst_bidx); in edma3_set_src_index()
199 src_dst_cidx = __raw_readl(&rg->src_dst_cidx); in edma3_set_src_index()
258 link_bcntrld = __raw_readl(&rg->link_bcntrld); in edma3_set_transfer_params()
263 opt = __raw_readl(&rg->opt); in edma3_set_transfer_params()
311 *p++ = __raw_readl(addr++); in edma3_read_slot()
359 if (!(__raw_readl(ipr_base) & inum)) in edma3_check_for_transfer()
/rk3399_rockchip-uboot/drivers/memory/
H A Dti-aemif.c43 tmp = __raw_readl(AEMIF_NAND_CONTROL); in aemif_configure()
48 tmp = __raw_readl(AEMIF_ONENAND_CONTROL); in aemif_configure()
53 tmp = __raw_readl(AEMIF_CONFIG(cs)); in aemif_configure()
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx5/
H A Dsoc.c30 int reg = __raw_readl(ROM_SI_REV); in get_cpu_rev()
38 if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0) in get_cpu_rev()
/rk3399_rockchip-uboot/arch/arm/mach-imx/
H A Dtimer.c79 i = __raw_readl(&cur_gpt->control); in timer_init()
112 return __raw_readl(&cur_gpt->counter); /* current tick value */ in timer_read_counter()
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx7/
H A Dclock_slice.c426 reg = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_set_src()
444 val = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_get_src()
482 reg = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_set_prediv()
512 val = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_get_prediv()
541 reg = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_set_postdiv()
561 val = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_get_postdiv()
597 val = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_set_autopostdiv()
637 val = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_get_autopostdiv()
656 *val = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_get_target_val()
738 val = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_root_enabled()
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc83xx/
H A Dcpu_init.c219 gd->arch.reset_status = __raw_readl(&im->reset.rsr); in cpu_init_f()
223 gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr); in cpu_init_f()
224 gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr); in cpu_init_f()
236 __raw_readl(&im->im_lbc.lcrr); in cpu_init_f()
325 temp = __raw_readl(&ehci->control); in cpu_init_f()
/rk3399_rockchip-uboot/board/imgtec/boston/
H A Dcheckboard.c24 changelist = __raw_readl((uint32_t *)BOSTON_PLAT_CORE_CL); in checkboard()
H A Dddr.c17 u32 ddrconf0 = __raw_readl((uint32_t *)BOSTON_PLAT_DDRCONF0); in dram_init()
/rk3399_rockchip-uboot/drivers/gpio/
H A Domap_gpio.c63 l = __raw_readl(reg); in _set_gpio_direction()
82 v = __raw_readl(reg); in _get_gpio_direction()
122 return (__raw_readl(reg) & (1 << gpio)) != 0; in _get_gpio_value()
/rk3399_rockchip-uboot/drivers/net/fsl-mc/dpio/
H A Dqbman_sys.h140 uint32_t reg = __raw_readl(s->addr_cinh + offset); in qbman_cinh_read()
196 shadow[loop] = __raw_readl(s->addr_cinh + offset in qbman_cena_read()
199 shadow[loop] = __raw_readl(s->addr_cena + offset in qbman_cena_read()
/rk3399_rockchip-uboot/drivers/pci/
H A Dpci_msc01.c53 *data = __raw_readl(cfgdata); in msc01_config_access()
56 if (__raw_readl(intstat) & aborts) { in msc01_config_access()
/rk3399_rockchip-uboot/drivers/usb/gadget/
H A Dat91_udc.c63 __raw_readl((udc)->udp_baseaddr + (reg))
138 csr = __raw_readl(creg); in read_fifo()
186 csr = __raw_readl(creg); in read_fifo()
200 u32 csr = __raw_readl(creg); in write_fifo()
222 csr = __raw_readl(creg); in write_fifo()
486 tmp = __raw_readl(ep->creg); in at91_ep_queue()
558 csr = __raw_readl(creg); in at91_ep_set_halt()
811 u32 csr = __raw_readl(creg); in handle_ep()
836 csr = __raw_readl(creg); in handle_ep()
897 csr = __raw_readl(creg); in handle_setup()
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