1*552a848eSStefano Babic /*
2*552a848eSStefano Babic * (C) Copyright 2007
3*552a848eSStefano Babic * Sascha Hauer, Pengutronix
4*552a848eSStefano Babic *
5*552a848eSStefano Babic * (C) Copyright 2009 Freescale Semiconductor, Inc.
6*552a848eSStefano Babic *
7*552a848eSStefano Babic * SPDX-License-Identifier: GPL-2.0+
8*552a848eSStefano Babic */
9*552a848eSStefano Babic
10*552a848eSStefano Babic #include <common.h>
11*552a848eSStefano Babic #include <asm/arch/imx-regs.h>
12*552a848eSStefano Babic #include <asm/arch/clock.h>
13*552a848eSStefano Babic #include <asm/arch/sys_proto.h>
14*552a848eSStefano Babic
15*552a848eSStefano Babic #include <linux/errno.h>
16*552a848eSStefano Babic #include <asm/io.h>
17*552a848eSStefano Babic #include <asm/mach-imx/boot_mode.h>
18*552a848eSStefano Babic
19*552a848eSStefano Babic #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
20*552a848eSStefano Babic #error "CPU_TYPE not defined"
21*552a848eSStefano Babic #endif
22*552a848eSStefano Babic
get_cpu_rev(void)23*552a848eSStefano Babic u32 get_cpu_rev(void)
24*552a848eSStefano Babic {
25*552a848eSStefano Babic #ifdef CONFIG_MX51
26*552a848eSStefano Babic int system_rev = 0x51000;
27*552a848eSStefano Babic #else
28*552a848eSStefano Babic int system_rev = 0x53000;
29*552a848eSStefano Babic #endif
30*552a848eSStefano Babic int reg = __raw_readl(ROM_SI_REV);
31*552a848eSStefano Babic
32*552a848eSStefano Babic #if defined(CONFIG_MX51)
33*552a848eSStefano Babic switch (reg) {
34*552a848eSStefano Babic case 0x02:
35*552a848eSStefano Babic system_rev |= CHIP_REV_1_1;
36*552a848eSStefano Babic break;
37*552a848eSStefano Babic case 0x10:
38*552a848eSStefano Babic if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
39*552a848eSStefano Babic system_rev |= CHIP_REV_2_5;
40*552a848eSStefano Babic else
41*552a848eSStefano Babic system_rev |= CHIP_REV_2_0;
42*552a848eSStefano Babic break;
43*552a848eSStefano Babic case 0x20:
44*552a848eSStefano Babic system_rev |= CHIP_REV_3_0;
45*552a848eSStefano Babic break;
46*552a848eSStefano Babic default:
47*552a848eSStefano Babic system_rev |= CHIP_REV_1_0;
48*552a848eSStefano Babic break;
49*552a848eSStefano Babic }
50*552a848eSStefano Babic #else
51*552a848eSStefano Babic if (reg < 0x20)
52*552a848eSStefano Babic system_rev |= CHIP_REV_1_0;
53*552a848eSStefano Babic else
54*552a848eSStefano Babic system_rev |= reg;
55*552a848eSStefano Babic #endif
56*552a848eSStefano Babic return system_rev;
57*552a848eSStefano Babic }
58*552a848eSStefano Babic
59*552a848eSStefano Babic #ifdef CONFIG_REVISION_TAG
get_board_rev(void)60*552a848eSStefano Babic u32 __weak get_board_rev(void)
61*552a848eSStefano Babic {
62*552a848eSStefano Babic return get_cpu_rev();
63*552a848eSStefano Babic }
64*552a848eSStefano Babic #endif
65*552a848eSStefano Babic
66*552a848eSStefano Babic #ifndef CONFIG_SYS_DCACHE_OFF
enable_caches(void)67*552a848eSStefano Babic void enable_caches(void)
68*552a848eSStefano Babic {
69*552a848eSStefano Babic /* Enable D-cache. I-cache is already enabled in start.S */
70*552a848eSStefano Babic dcache_enable();
71*552a848eSStefano Babic }
72*552a848eSStefano Babic #endif
73*552a848eSStefano Babic
74*552a848eSStefano Babic #if defined(CONFIG_FEC_MXC)
imx_get_mac_from_fuse(int dev_id,unsigned char * mac)75*552a848eSStefano Babic void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
76*552a848eSStefano Babic {
77*552a848eSStefano Babic int i;
78*552a848eSStefano Babic struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
79*552a848eSStefano Babic struct fuse_bank *bank = &iim->bank[1];
80*552a848eSStefano Babic struct fuse_bank1_regs *fuse =
81*552a848eSStefano Babic (struct fuse_bank1_regs *)bank->fuse_regs;
82*552a848eSStefano Babic
83*552a848eSStefano Babic for (i = 0; i < 6; i++)
84*552a848eSStefano Babic mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
85*552a848eSStefano Babic }
86*552a848eSStefano Babic #endif
87*552a848eSStefano Babic
88*552a848eSStefano Babic #ifdef CONFIG_MX53
boot_mode_apply(unsigned cfg_val)89*552a848eSStefano Babic void boot_mode_apply(unsigned cfg_val)
90*552a848eSStefano Babic {
91*552a848eSStefano Babic writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
92*552a848eSStefano Babic }
93*552a848eSStefano Babic /*
94*552a848eSStefano Babic * cfg_val will be used for
95*552a848eSStefano Babic * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
96*552a848eSStefano Babic *
97*552a848eSStefano Babic * If bit 28 of LPGR is set upon watchdog reset,
98*552a848eSStefano Babic * bits[25:0] of LPGR will move to SBMR.
99*552a848eSStefano Babic */
100*552a848eSStefano Babic const struct boot_mode soc_boot_modes[] = {
101*552a848eSStefano Babic {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
102*552a848eSStefano Babic /* usb or serial download */
103*552a848eSStefano Babic {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
104*552a848eSStefano Babic {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
105*552a848eSStefano Babic {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
106*552a848eSStefano Babic {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
107*552a848eSStefano Babic {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
108*552a848eSStefano Babic {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
109*552a848eSStefano Babic /* 4 bit bus width */
110*552a848eSStefano Babic {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
111*552a848eSStefano Babic {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
112*552a848eSStefano Babic {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
113*552a848eSStefano Babic {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
114*552a848eSStefano Babic {NULL, 0},
115*552a848eSStefano Babic };
116*552a848eSStefano Babic #endif
117