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Searched refs:CONFIG_SYS_SDRAM_BASE (Results 1 – 25 of 562) sorted by relevance

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/rk3399_rockchip-uboot/include/configs/
H A Dexynos7420-common.h51 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
53 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
55 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
57 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
59 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
61 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
63 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
65 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
67 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
H A Dexynos5-common.h54 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
55 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
56 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
60 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
62 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
64 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
66 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
68 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
70 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
72 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
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H A Dsmdkv310.h25 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
51 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
52 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
53 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
58 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
60 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
62 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
64 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
H A Dboston.h28 # define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 macro
30 # define CONFIG_SYS_SDRAM_BASE 0x80000000 macro
37 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000)
39 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0)
40 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x10000000)
H A Dsmdkc100.h32 #define CONFIG_SYS_SDRAM_BASE 0x30000000 macro
121 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
122 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5e00000)
123 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
127 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
145 #define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE
H A Dorigen.h22 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
23 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
27 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
28 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
29 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
H A Dmalta.h39 # define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 macro
41 # define CONFIG_SYS_SDRAM_BASE 0x80000000 macro
47 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000)
48 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
49 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x00800000)
H A Dodroid.h26 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
28 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
34 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
35 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
36 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
H A Dtrats.h27 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
28 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
33 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
34 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
35 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
168 #define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100
H A Dat91rm9200ek.h63 #define CONFIG_SYS_SDRAM_BASE 0x20000000 macro
66 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
91 #define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
92 #define CONFIG_SYS_SDRAM1 (CONFIG_SYS_SDRAM_BASE+0x80)
168 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M
184 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
H A Dr2dplus.h17 #define CONFIG_SYS_SDRAM_BASE 0x8C000000 macro
24 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
27 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
86 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
87 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
H A Ds5pc210_universal.h22 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
23 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
43 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
44 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
45 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
H A Dtrats2.h26 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
27 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
30 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
31 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
32 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
H A Dr7780mp.h25 #define CONFIG_SYS_SDRAM_BASE (0x08000000) macro
31 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
52 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
98 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
99 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
H A Ds5p_goni.h29 #define CONFIG_SYS_SDRAM_BASE 0x30000000 macro
173 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
174 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
175 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000000)
179 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */
H A Dmeesc.h68 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM macro
71 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
72 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000)
73 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000)
H A Dstmark2.h109 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
129 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
132 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
158 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
183 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
H A Dwork_92105.h38 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE macro
41 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
44 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
46 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
H A DM5235EVB.h98 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
124 #define CONFIG_SYS_SDRAM_BASE 0x00000000 macro
127 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
142 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
192 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
H A Dbcm_ep_board.h21 #ifndef CONFIG_SYS_SDRAM_BASE
22 #error CONFIG_SYS_SDRAM_BASE must be defined!
33 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
H A D10m50_devboard.h54 #define CONFIG_SYS_SDRAM_BASE 0xc8000000 macro
59 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \
82 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
/rk3399_rockchip-uboot/board/freescale/m5275evb/
H A Dm5275evb.c37 out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE); in dram_init()
51 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
57 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
61 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
68 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
73 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
74 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
78 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
/rk3399_rockchip-uboot/arch/arm/mach-at91/arm926ejs/
H A Dlowlevel_init.S205 .word CONFIG_SYS_SDRAM_BASE
209 .word CONFIG_SYS_SDRAM_BASE
211 .word CONFIG_SYS_SDRAM_BASE
213 .word CONFIG_SYS_SDRAM_BASE
215 .word CONFIG_SYS_SDRAM_BASE
217 .word CONFIG_SYS_SDRAM_BASE
219 .word CONFIG_SYS_SDRAM_BASE
221 .word CONFIG_SYS_SDRAM_BASE
223 .word CONFIG_SYS_SDRAM_BASE
227 .word CONFIG_SYS_SDRAM_BASE
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/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Ddram_helpers.c33 writel(0, CONFIG_SYS_SDRAM_BASE); in mctl_mem_matches()
34 writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); in mctl_mem_matches()
37 return readl(CONFIG_SYS_SDRAM_BASE) == in mctl_mem_matches()
38 readl((ulong)CONFIG_SYS_SDRAM_BASE + offset); in mctl_mem_matches()
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_common.c264 writel(0, CONFIG_SYS_SDRAM_BASE); in sdram_detect_col()
265 test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + in sdram_detect_col()
269 (readl(CONFIG_SYS_SDRAM_BASE) == 0)) in sdram_detect_col()
292 test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + in sdram_detect_bank()
294 writel(0, CONFIG_SYS_SDRAM_BASE); in sdram_detect_bank()
300 (readl(CONFIG_SYS_SDRAM_BASE) == 0)) in sdram_detect_bank()
324 test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + in sdram_detect_bg()
326 writel(0, CONFIG_SYS_SDRAM_BASE); in sdram_detect_bg()
332 (readl(CONFIG_SYS_SDRAM_BASE) == 0)) in sdram_detect_bg()
403 writel(0, CONFIG_SYS_SDRAM_BASE); in sdram_detect_row()
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