1e21185baSChander Kashyap /* 2e21185baSChander Kashyap * Copyright (C) 2011 Samsung Electronics 3e21185baSChander Kashyap * 4393cb361SChander Kashyap * Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board. 5e21185baSChander Kashyap * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 7e21185baSChander Kashyap */ 8e21185baSChander Kashyap 9e21185baSChander Kashyap #ifndef __CONFIG_H 10e21185baSChander Kashyap #define __CONFIG_H 11e21185baSChander Kashyap 121d551100SSimon Glass #include "exynos4-common.h" 131d551100SSimon Glass 141d551100SSimon Glass #undef CONFIG_BOARD_COMMON 15e30824f4SMarek Vasut #undef CONFIG_USB_GADGET_DWC2_OTG_PHY 161d551100SSimon Glass #undef CONFIG_REVISION_TAG 171d551100SSimon Glass 18e21185baSChander Kashyap /* High Level Configuration Options */ 19393cb361SChander Kashyap #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ 20e21185baSChander Kashyap #define CONFIG_SMDKV310 1 /* working with SMDKV310*/ 21e21185baSChander Kashyap 22b3c5a49bSChander Kashyap /* Mach Type */ 23b3c5a49bSChander Kashyap #define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310 24b3c5a49bSChander Kashyap 25e21185baSChander Kashyap #define CONFIG_SYS_SDRAM_BASE 0x40000000 26e21185baSChander Kashyap #define CONFIG_SYS_TEXT_BASE 0x43E00000 27e21185baSChander Kashyap 28e21185baSChander Kashyap /* Handling Sleep Mode*/ 29e21185baSChander Kashyap #define S5P_CHECK_SLEEP 0x00000BAD 30e21185baSChander Kashyap #define S5P_CHECK_DIDLE 0xBAD00000 31643be9c0SRajeshwari Shinde #define S5P_CHECK_LPA 0xABAD0000 32e21185baSChander Kashyap 33e21185baSChander Kashyap /* select serial console configuration */ 34e21185baSChander Kashyap #define CONFIG_SERIAL1 1 /* use SERIAL 1 */ 35393cb361SChander Kashyap #define EXYNOS4_DEFAULT_UART_OFFSET 0x010000 36e21185baSChander Kashyap 37e21185baSChander Kashyap /* allow to overwrite serial and ethaddr */ 38e21185baSChander Kashyap #define CONFIG_ENV_OVERWRITE 39e21185baSChander Kashyap 405187d8ddSChander Kashyap /* MMC SPL */ 41643be9c0SRajeshwari Shinde #define CONFIG_SKIP_LOWLEVEL_INIT 429b3ab1c9SChander Kashyap #define COPY_BL2_FNPTR_ADDR 0x00002488 43e21185baSChander Kashyap 448a00061eSInderpal Singh #define CONFIG_SPL_TEXT_BASE 0x02021410 458a00061eSInderpal Singh 46e21185baSChander Kashyap #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" 47e21185baSChander Kashyap 48e21185baSChander Kashyap /* Miscellaneous configurable options */ 49e21185baSChander Kashyap #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" 50e21185baSChander Kashyap /* memtest works on */ 51e21185baSChander Kashyap #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 52e21185baSChander Kashyap #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) 53e21185baSChander Kashyap #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) 54e21185baSChander Kashyap 55e21185baSChander Kashyap /* SMDKV310 has 4 bank of DRAM */ 56e21185baSChander Kashyap #define CONFIG_NR_DRAM_BANKS 4 57e21185baSChander Kashyap #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ 58e21185baSChander Kashyap #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 59e21185baSChander Kashyap #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE 60e21185baSChander Kashyap #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) 61e21185baSChander Kashyap #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE 62e21185baSChander Kashyap #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) 63e21185baSChander Kashyap #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE 64e21185baSChander Kashyap #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) 65e21185baSChander Kashyap #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE 66e21185baSChander Kashyap 67e21185baSChander Kashyap /* FLASH and environment organization */ 68e21185baSChander Kashyap 69e21185baSChander Kashyap #define CONFIG_CLK_1000_400_200 70e21185baSChander Kashyap 71e21185baSChander Kashyap /* MIU (Memory Interleaving Unit) */ 72e21185baSChander Kashyap #define CONFIG_MIU_2BIT_INTERLEAVED 73e21185baSChander Kashyap 74e21185baSChander Kashyap #define CONFIG_SYS_MMC_ENV_DEV 0 75e21185baSChander Kashyap #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ 76e21185baSChander Kashyap #define RESERVE_BLOCK_SIZE (512) 77e21185baSChander Kashyap #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ 78e21185baSChander Kashyap #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) 79e21185baSChander Kashyap 80643be9c0SRajeshwari Shinde #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) 81643be9c0SRajeshwari Shinde 82643be9c0SRajeshwari Shinde #define CONFIG_SYS_INIT_SP_ADDR 0x02040000 83e21185baSChander Kashyap 84*a187559eSBin Meng /* U-Boot copy size from boot Media to DRAM.*/ 85e21185baSChander Kashyap #define COPY_BL2_SIZE 0x80000 86e21185baSChander Kashyap #define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) 87e21185baSChander Kashyap #define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) 88e21185baSChander Kashyap 89e21185baSChander Kashyap /* Ethernet Controllor Driver */ 90e21185baSChander Kashyap #ifdef CONFIG_CMD_NET 91e21185baSChander Kashyap #define CONFIG_SMC911X 92e21185baSChander Kashyap #define CONFIG_SMC911X_BASE 0x5000000 93e21185baSChander Kashyap #define CONFIG_SMC911X_16_BIT 94e21185baSChander Kashyap #define CONFIG_ENV_SROM_BANK 1 95e21185baSChander Kashyap #endif /*CONFIG_CMD_NET*/ 9607407d97SThomas Abraham 97e21185baSChander Kashyap #endif /* __CONFIG_H */ 98