1e6e505b9SAlexander Graf /* 2e6e505b9SAlexander Graf * DRAM init helper functions 3e6e505b9SAlexander Graf * 4e6e505b9SAlexander Graf * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> 5e6e505b9SAlexander Graf * 6e6e505b9SAlexander Graf * SPDX-License-Identifier: GPL-2.0+ 7e6e505b9SAlexander Graf */ 8e6e505b9SAlexander Graf 9e6e505b9SAlexander Graf #include <common.h> 101ea4fac5SAndre Przywara #include <asm/barriers.h> 11e6e505b9SAlexander Graf #include <asm/io.h> 12e6e505b9SAlexander Graf #include <asm/arch/dram.h> 13e6e505b9SAlexander Graf 14e6e505b9SAlexander Graf /* 15e6e505b9SAlexander Graf * Wait up to 1s for value to be set in given part of reg. 16e6e505b9SAlexander Graf */ mctl_await_completion(u32 * reg,u32 mask,u32 val)17e6e505b9SAlexander Grafvoid mctl_await_completion(u32 *reg, u32 mask, u32 val) 18e6e505b9SAlexander Graf { 19e6e505b9SAlexander Graf unsigned long tmo = timer_get_us() + 1000000; 20e6e505b9SAlexander Graf 21e6e505b9SAlexander Graf while ((readl(reg) & mask) != val) { 22e6e505b9SAlexander Graf if (timer_get_us() > tmo) 23e6e505b9SAlexander Graf panic("Timeout initialising DRAM\n"); 24e6e505b9SAlexander Graf } 25e6e505b9SAlexander Graf } 26e6e505b9SAlexander Graf 27e6e505b9SAlexander Graf /* 28e6e505b9SAlexander Graf * Test if memory at offset offset matches memory at begin of DRAM 29e6e505b9SAlexander Graf */ mctl_mem_matches(u32 offset)30e6e505b9SAlexander Grafbool mctl_mem_matches(u32 offset) 31e6e505b9SAlexander Graf { 32e6e505b9SAlexander Graf /* Try to write different values to RAM at two addresses */ 33e6e505b9SAlexander Graf writel(0, CONFIG_SYS_SDRAM_BASE); 340ea5a04fSAlexander Graf writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); 35*a78cd861STom Rini dsb(); 36e6e505b9SAlexander Graf /* Check if the same value is actually observed when reading back */ 37e6e505b9SAlexander Graf return readl(CONFIG_SYS_SDRAM_BASE) == 380ea5a04fSAlexander Graf readl((ulong)CONFIG_SYS_SDRAM_BASE + offset); 39e6e505b9SAlexander Graf } 40