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/rk3399_ARM-atf/plat/arm/board/automotive_rd/platform/rd1ae/include/
H A Drd1ae_helpers.S29 mov x4, x0
32 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
33 ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
34 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
35 ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
38 mov x4, #PLAT_ARM_CLUSTER_COUNT
39 madd x2, x3, x4, x2
40 mov x4, #PLAT_MAX_CPUS_PER_CLUSTER
41 madd x1, x2, x4, x1
42 mov x4, #PLAT_MAX_PE_PER_CPU
[all …]
/rk3399_ARM-atf/plat/arm/board/morello/aarch64/
H A Dmorello_helper.S34 mov x4, x0
42 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
43 ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
44 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
45 ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
48 mov x4, #MORELLO_MAX_CLUSTERS_PER_CHIP
49 madd x2, x3, x4, x2
50 mov x4, #MORELLO_MAX_CPUS_PER_CLUSTER
51 madd x1, x2, x4, x1
52 mov x4, #MORELLO_MAX_PE_PER_CPU
[all …]
/rk3399_ARM-atf/plat/arm/board/n1sdp/aarch64/
H A Dn1sdp_helper.S33 mov x4, x0
41 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
42 ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
43 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
44 ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
47 mov x4, #N1SDP_MAX_CLUSTERS_PER_CHIP
48 madd x2, x3, x4, x2
49 mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER
50 madd x1, x2, x4, x1
51 mov x4, #N1SDP_MAX_PE_PER_CPU
[all …]
/rk3399_ARM-atf/plat/nxp/common/psci/aarch64/
H A Dpsci_utils.S36 stp x4, x5, [sp, #-16]!
193 ldp x4, x5, [sp], #16
218 stp x4, x5, [sp, #-16]!
237 mrs x4, CPUECTLR_EL1
239 mov x2, x4
244 bic x4, x4, #CPUECTLR_SMPEN_MASK
245 msr CPUECTLR_EL1, x4
249 mrs x4, SCR_EL3
250 mov x2, x4
257 orr x4, x4, #SCR_FIQ_MASK
[all …]
/rk3399_ARM-atf/plat/intel/soc/common/aarch64/
H A Dplat_helpers.S49 mrs x4, mpidr_el1
50 and x4, x4, #0xff
51 cmp x3, x4
105 ldr x4, =L2_RESET_DONE_REG
106 tst x4, #ALIGN_CHECK_64BIT_MASK
109 str x2, [x4]
114 strb w2, [x4]
116 add x4, x4, #1
117 strb w2, [x4]
119 add x4, x4, #1
[all …]
/rk3399_ARM-atf/plat/arm/board/arm_fpga/
H A Dkernel_trampoline.S32 adr x4, _tramp_start
33 orr x4, x4, #0x1fffff
34 add x4, x4, #1 /* align up to 2MB */
35 br x4
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/arch/aarch64/
H A Dnrd_helper.S38 mov x4, x0
46 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
47 ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
48 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
49 ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
52 mov x4, #PLAT_ARM_CLUSTER_COUNT
53 madd x2, x3, x4, x2
54 mov x4, #NRD_MAX_CPUS_PER_CLUSTER
55 madd x1, x2, x4, x1
56 mov x4, #NRD_MAX_PE_PER_CPU
[all …]
/rk3399_ARM-atf/common/aarch64/
H A Ddebug.S42 udiv x0, x4, x5 /* Get the quotient */
43 msub x4, x0, x5, x4 /* Find the remainder */
76 adr x4, assert_msg1
78 mov x4, x5
80 adr x4, assert_msg2
86 mov x4, x6
103 ldrb w0, [x4], #0x1
124 lsrv x0, x4, x5
183 adr x4, panic_msg
185 mov x4, x6
[all …]
/rk3399_ARM-atf/services/std_svc/
H A Dstd_svc_setup.c118 u_register_t x4 = x4_arg; in std_svc_smc_handler() local
126 x4 &= UINT32_MAX; in std_svc_smc_handler()
148 ret = psci_smc_handler(smc_fid, x1, x2, x3, x4, in std_svc_smc_handler()
166 return spm_mm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
177 return spmd_ffa_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
184 return sdei_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
191 return trng_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
198 return errata_abi_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
206 return rmmd_rmm_el3_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
211 return rmmd_rmi_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
[all …]
/rk3399_ARM-atf/plat/nxp/soc-ls1043a/aarch64/
H A Dls1043a.S163 mov x4, x0
167 ldr w1, [x4, #GICD_CTLR_OFFSET]
169 str w1, [x4, #GICD_CTLR_OFFSET]
182 str w1, [x4, #GICD_SGIR_OFFSET]
307 orr x4, x5, #DEVDISR5_I2C_1
309 csel x5, x5, x4, EQ
311 orr x4, x5, #DEVDISR5_LPUART1
313 csel x5, x5, x4, EQ
315 orr x4, x5, #DEVDISR5_FLX_TMR
317 csel x5, x5, x4, EQ
[all …]
/rk3399_ARM-atf/include/plat/arm/common/aarch64/
H A Darm_macros.S82 adr x4, gicd_pend_reg
85 sub x4, x7, x16
86 cmp x4, #0x280
90 adr x4, prefix
94 sub x4, x7, x16
98 adr x4, spacer
101 ldr x4, [x7], #8
104 adr x4, newline
/rk3399_ARM-atf/plat/hisilicon/hikey/aarch64/
H A Dhikey_helpers.S105 adr x4, plat_err_str
108 adr x4, esr_el3_str
111 mrs x4, esr_el3
114 adr x4, elr_el3_str
117 mrs x4, elr_el3
122 adr x4, plat_err_str
125 adr x4, esr_el1_str
128 mrs x4, esr_el1
131 adr x4, elr_el1_str
134 mrs x4, elr_el1
/rk3399_ARM-atf/plat/amlogic/common/include/
H A Dplat_macros.S49 adr x4, gicd_pend_reg
53 sub x4, x7, x16
54 cmp x4, #0x280
58 adr x4, spacer
61 ldr x4, [x7], #8
64 adr x4, newline
/rk3399_ARM-atf/plat/renesas/common/include/
H A Dplat_macros_gic.S45 adr x4, gicd_pend_reg
48 sub x4, x7, x16
49 cmp x4, #0x280
52 adr x4, spacer
54 ldr x4, [x7], #8
56 adr x4, newline
/rk3399_ARM-atf/plat/hisilicon/hikey960/aarch64/
H A Dhikey960_helpers.S109 adr x4, plat_err_str
112 adr x4, esr_el3_str
115 mrs x4, esr_el3
118 adr x4, elr_el3_str
121 mrs x4, elr_el3
126 adr x4, plat_err_str
129 adr x4, esr_el1_str
132 mrs x4, esr_el1
135 adr x4, elr_el1_str
138 mrs x4, elr_el1
/rk3399_ARM-atf/bl31/aarch64/
H A Dcrash_reporting.S99 mov x4, x6
103 sub x0, x4, x6
105 mov x6, x4
108 ldr x4, [x7], #REGSZ
113 ldr x4, [x7], #REGSZ
133 adr x4, print_spacer - 3
134 add x4, x4, x0
241 adr x4, excpt_msg_el
253 mov x4, x6
257 sub x0, x4, x6
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8186/
H A Dplat_sip_calls.c20 u_register_t x4, in mediatek_plat_sip_handler() argument
30 ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4); in mediatek_plat_sip_handler()
31 SMC_RET2(handle, ret, x4); in mediatek_plat_sip_handler()
35 ret = dfd_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()
40 ret = msdc_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()
/rk3399_ARM-atf/plat/mediatek/common/
H A Dmtk_sip_svc.c29 u_register_t x4, in mediatek_plat_sip_handler() argument
44 u_register_t x4, in mediatek_sip_handler() argument
52 clean_top_32b_of_param(smc_fid, &x1, &x2, &x3, &x4); in mediatek_sip_handler()
74 boot_to_kernel(x1, x2, x3, x4); in mediatek_sip_handler()
83 return mediatek_plat_sip_handler(smc_fid, x1, x2, x3, x4, in mediatek_sip_handler()
95 u_register_t x4, in sip_smc_handler() argument
116 return mediatek_sip_handler(smc_fid, x1, x2, x3, x4, in sip_smc_handler()
/rk3399_ARM-atf/plat/mediatek/mt8192/
H A Dplat_sip_calls.c19 u_register_t x4, in mediatek_plat_sip_handler() argument
30 ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4); in mediatek_plat_sip_handler()
31 SMC_RET2(handle, ret, x4); in mediatek_plat_sip_handler()
35 ret = apusys_kernel_ctrl(x1, x2, x3, x4, &rnd_val0); in mediatek_plat_sip_handler()
40 ret = dfd_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()
/rk3399_ARM-atf/lib/xlat_tables_v2/aarch64/
H A Denable_mmu.S72 _mrs x4, sctlr, \el
74 orr x4, x4, x5
77 bic x5, x4, #SCTLR_C_BIT
79 csel x4, x5, x4, ne
81 _msr sctlr, \el, x4
/rk3399_ARM-atf/plat/hisilicon/hikey960/include/
H A Dplat_macros.S50 adr x4, gicd_pend_reg
53 sub x4, x7, x16
54 cmp x4, #0x280
57 adr x4, spacer
59 ldr x4, [x7], #8
61 adr x4, newline
/rk3399_ARM-atf/plat/hisilicon/hikey/include/
H A Dplat_macros.S50 adr x4, gicd_pend_reg
53 sub x4, x7, x16
54 cmp x4, #0x280
57 adr x4, spacer
59 ldr x4, [x7], #8
61 adr x4, newline
/rk3399_ARM-atf/plat/mediatek/mt8183/include/
H A Dplat_macros.S48 adr x4, gicd_pend_reg
51 sub x4, x7, x26
52 cmp x4, #0x280
56 adr x4, spacer
59 ldr x4, [x7], #8
62 adr x4, newline
/rk3399_ARM-atf/plat/mediatek/mt8173/include/
H A Dplat_macros.S48 adr x4, gicd_pend_reg
51 sub x4, x7, x16
52 cmp x4, #0x280
56 adr x4, spacer
59 ldr x4, [x7], #8
62 adr x4, newline
/rk3399_ARM-atf/plat/nxp/soc-ls1046a/aarch64/
H A Dls1046a.S142 mov x4, x0
145 ldr w1, [x4, #GICD_CTLR_OFFSET]
147 str w1, [x4, #GICD_CTLR_OFFSET]
162 str w1, [x4, #GICD_SGIR_OFFSET]
352 mrs x4, CORTEX_A72_ECTLR_EL1
353 bic x4, x4, #CPUECTLR_RET_MASK
354 orr x4, x4, #CPUECTLR_TIMER_8TICKS
355 orr x4, x4, #CPUECTLR_SMPEN_EN
356 msr CORTEX_A72_ECTLR_EL1, x4
386 ldr x4, =SCFG_RETREQCR_OFFSET
[all …]

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