1*de9fdb9bSAndre Przywara/* 2*de9fdb9bSAndre Przywara * Copyright (c) 2021, ARM Limited. All rights reserved. 3*de9fdb9bSAndre Przywara * 4*de9fdb9bSAndre Przywara * SPDX-License-Identifier: BSD-3-Clause 5*de9fdb9bSAndre Przywara * 6*de9fdb9bSAndre Przywara * The traditional arm64 Linux kernel load address is 512KiB from the 7*de9fdb9bSAndre Przywara * beginning of DRAM, caused by this having been the default value of the 8*de9fdb9bSAndre Przywara * kernel's CONFIG_TEXT_OFFSET Kconfig value. 9*de9fdb9bSAndre Przywara * However kernel version 5.8 changed the default offset (into a 2MB page) 10*de9fdb9bSAndre Przywara * to 0, so TF-A's default assumption is no longer true. Fortunately the 11*de9fdb9bSAndre Przywara * kernel got more relaxed about this offset at the same time, so it 12*de9fdb9bSAndre Przywara * tolerates the wrong offset, but issues a warning: 13*de9fdb9bSAndre Przywara * [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader! 14*de9fdb9bSAndre Przywara * 15*de9fdb9bSAndre Przywara * We cannot easily change the load address offset in TF-A to be 2MiB, because 16*de9fdb9bSAndre Przywara * this would break older kernels - and they are not as forgiving in this 17*de9fdb9bSAndre Przywara * respect. 18*de9fdb9bSAndre Przywara * 19*de9fdb9bSAndre Przywara * But we can allow users to load the kernel at the right offset, and 20*de9fdb9bSAndre Przywara * offer this trampoline here to transition to this new load address. 21*de9fdb9bSAndre Przywara * Any older kernels, or newer kernels misloaded, will overwrite this code 22*de9fdb9bSAndre Przywara * here, so it does no harm in this case. 23*de9fdb9bSAndre Przywara */ 24*de9fdb9bSAndre Przywara 25*de9fdb9bSAndre Przywara#include <asm_macros.S> 26*de9fdb9bSAndre Przywara#include <common/bl_common.ld.h> 27*de9fdb9bSAndre Przywara 28*de9fdb9bSAndre Przywara.text 29*de9fdb9bSAndre Przywara.global _tramp_start 30*de9fdb9bSAndre Przywara 31*de9fdb9bSAndre Przywara_tramp_start: 32*de9fdb9bSAndre Przywara adr x4, _tramp_start 33*de9fdb9bSAndre Przywara orr x4, x4, #0x1fffff 34*de9fdb9bSAndre Przywara add x4, x4, #1 /* align up to 2MB */ 35*de9fdb9bSAndre Przywara br x4 36