| /rk3399_ARM-atf/plat/arm/common/aarch64/ |
| H A D | execution_state_switch.c | 43 u_register_t spsr, pc, scr, sctlr; in arm_execution_state_switch() local
61 spsr = read_ctx_reg(el3_ctx, CTX_SPSR_EL3); in arm_execution_state_switch()
62 caller_64 = (GET_RW(spsr) == MODE_RW_64); in arm_execution_state_switch()
93 from_el2 = caller_64 ? (GET_EL(spsr) == MODE_EL2) : in arm_execution_state_switch()
94 (GET_M32(spsr) == MODE32_hyp); in arm_execution_state_switch()
129 spsr = SPSR_MODE32((u_register_t) el, in arm_execution_state_switch()
139 spsr = SPSR_64((u_register_t) el, MODE_SP_ELX, in arm_execution_state_switch()
153 ep.spsr = (uint32_t) spsr; in arm_execution_state_switch()
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| /rk3399_ARM-atf/plat/hisilicon/poplar/ |
| H A D | bl2_plat_setup.c | 65 uint32_t spsr; in poplar_get_spsr_for_bl33_entry() local
78 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in poplar_get_spsr_for_bl33_entry()
79 return spsr; in poplar_get_spsr_for_bl33_entry()
84 unsigned int hyp_status, mode, spsr; in poplar_get_spsr_for_bl33_entry() local
95 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, in poplar_get_spsr_for_bl33_entry()
97 return spsr; in poplar_get_spsr_for_bl33_entry()
136 bl_mem_params->ep_info.spsr = poplar_get_spsr_for_bl32_entry(); in poplar_bl2_handle_post_image_load()
143 bl_mem_params->ep_info.spsr = poplar_get_spsr_for_bl33_entry(); in poplar_bl2_handle_post_image_load()
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| /rk3399_ARM-atf/plat/imx/common/ |
| H A D | imx_bl31_common.c | 13 uint32_t spsr; in plat_get_spsr_for_bl33_entry() local
21 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in plat_get_spsr_for_bl33_entry()
22 return spsr; in plat_get_spsr_for_bl33_entry()
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| /rk3399_ARM-atf/plat/intel/soc/common/aarch64/ |
| H A D | platform_common.c | 38 uint32_t spsr; in socfpga_get_spsr_for_bl33_entry() local
51 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in socfpga_get_spsr_for_bl33_entry()
52 return spsr; in socfpga_get_spsr_for_bl33_entry()
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| /rk3399_ARM-atf/plat/brcm/common/ |
| H A D | brcm_common.c | 42 uint32_t spsr; in brcm_get_spsr_for_bl33_entry() local
52 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in brcm_get_spsr_for_bl33_entry()
53 return spsr; in brcm_get_spsr_for_bl33_entry()
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| /rk3399_ARM-atf/services/spd/trusty/ |
| H A D | trusty.c | 478 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, in trusty_setup()
481 ep_info->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, in trusty_setup()
507 uint32_t spsr; in trusty_setup() local
514 spsr = ns_ep_info->spsr; in trusty_setup()
515 if (GET_RW(spsr) == MODE_RW_64 && GET_EL(spsr) == MODE_EL2) { in trusty_setup()
516 spsr &= ~(MODE_EL_MASK << MODE_EL_SHIFT); in trusty_setup()
517 spsr |= MODE_EL1 << MODE_EL_SHIFT; in trusty_setup()
519 if (GET_RW(spsr) == MODE_RW_32 && GET_M32(spsr) == MODE32_hyp) { in trusty_setup()
520 spsr &= ~(MODE32_MASK << MODE32_SHIFT); in trusty_setup()
521 spsr |= MODE32_svc << MODE32_SHIFT; in trusty_setup()
[all …]
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| /rk3399_ARM-atf/plat/nxp/common/setup/ |
| H A D | ls_bl2_el3_setup.c | 107 uint32_t spsr; in ls_get_spsr_for_bl33_entry() local
117 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in ls_get_spsr_for_bl33_entry()
118 return spsr; in ls_get_spsr_for_bl33_entry()
126 unsigned int hyp_status, mode, spsr; in ls_get_spsr_for_bl33_entry() local
137 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, in ls_get_spsr_for_bl33_entry()
139 return spsr; in ls_get_spsr_for_bl33_entry()
247 bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl32_entry(); in ls_bl2_handle_post_image_load()
253 bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl33_entry(); in ls_bl2_handle_post_image_load()
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| /rk3399_ARM-atf/services/spd/tlkd/ |
| H A D | tlkd_common.c | 85 uint32_t ep_attr, spsr; in tlkd_init_tlk_ep_state() local
98 spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in tlkd_init_tlk_ep_state()
100 spsr = SPSR_MODE32(MODE32_svc, in tlkd_init_tlk_ep_state()
112 tlk_entry_point->spsr = spsr; in tlkd_init_tlk_ep_state()
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| /rk3399_ARM-atf/plat/hisilicon/hikey/ |
| H A D | hikey_bl2_setup.c | 85 uint32_t spsr; in hikey_get_spsr_for_bl33_entry() local
95 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in hikey_get_spsr_for_bl33_entry()
96 return spsr; in hikey_get_spsr_for_bl33_entry()
101 unsigned int hyp_status, mode, spsr; in hikey_get_spsr_for_bl33_entry() local
112 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, in hikey_get_spsr_for_bl33_entry()
114 return spsr; in hikey_get_spsr_for_bl33_entry()
150 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl32_entry(); in hikey_bl2_handle_post_image_load()
157 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl33_entry(); in hikey_bl2_handle_post_image_load()
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| /rk3399_ARM-atf/plat/imx/imx93/ |
| H A D | imx93_bl31_setup.c | 47 uint32_t spsr; in get_spsr_for_bl33_entry() local
55 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in get_spsr_for_bl33_entry()
56 return spsr; in get_spsr_for_bl33_entry()
75 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); in bl31_early_platform_setup2()
83 bl32_image_ep_info.spsr = 0; in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/plat/ti/common/ |
| H A D | ti_bl31_setup.c | 36 uint32_t spsr; in k3_get_spsr_for_bl33_entry() local
44 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in k3_get_spsr_for_bl33_entry()
45 return spsr; in k3_get_spsr_for_bl33_entry()
62 bl32_image_ep_info.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, in bl31_early_platform_setup2()
70 bl33_image_ep_info.spsr = k3_get_spsr_for_bl33_entry(); in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/ |
| H A D | plat_bl31_setup.c | 22 uint32_t spsr; in get_spsr_for_bl33_entry() local
24 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in get_spsr_for_bl33_entry()
26 return spsr; in get_spsr_for_bl33_entry()
34 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/plat/hisilicon/hikey960/ |
| H A D | hikey960_bl2_setup.c | 179 uint32_t spsr; in hikey960_get_spsr_for_bl33_entry() local
189 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in hikey960_get_spsr_for_bl33_entry()
190 return spsr; in hikey960_get_spsr_for_bl33_entry()
195 unsigned int hyp_status, mode, spsr; in hikey960_get_spsr_for_bl33_entry() local
206 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, in hikey960_get_spsr_for_bl33_entry()
208 return spsr; in hikey960_get_spsr_for_bl33_entry()
244 bl_mem_params->ep_info.spsr = hikey960_get_spsr_for_bl32_entry(); in hikey960_bl2_handle_post_image_load()
251 bl_mem_params->ep_info.spsr = hikey960_get_spsr_for_bl33_entry(); in hikey960_bl2_handle_post_image_load()
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| /rk3399_ARM-atf/plat/marvell/armada/common/aarch64/ |
| H A D | marvell_common.c | 112 uint32_t spsr; in marvell_get_spsr_for_bl33_entry() local
125 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in marvell_get_spsr_for_bl33_entry()
126 return spsr; in marvell_get_spsr_for_bl33_entry()
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| /rk3399_ARM-atf/include/arch/aarch32/ |
| H A D | smccc_macros.S | 36 mrs r2, spsr
40 mrs r2, spsr
44 mrs r2, spsr
48 mrs r2, spsr
52 mrs r2, spsr
57 mrs r2, spsr
82 mrs r12, spsr
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| /rk3399_ARM-atf/plat/socionext/synquacer/ |
| H A D | sq_image_desc.c | 27 .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
44 .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
61 .ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
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| H A D | sq_bl31_setup.c | 95 uint32_t spsr; in sq_get_spsr_for_bl33_entry() local
103 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in sq_get_spsr_for_bl33_entry()
104 return spsr; in sq_get_spsr_for_bl33_entry()
142 bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry(); in bl31_early_platform_setup2()
158 bl33_image_ep_info.spsr = sq_get_spsr_for_bl33_entry(); in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/plat/qti/common/src/ |
| H A D | qti_image_desc.c | 27 .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
44 .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
61 .ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
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| /rk3399_ARM-atf/plat/arm/common/ |
| H A D | arm_common.c | 78 unsigned int __unused hyp_status, mode, spsr; in arm_get_spsr() local
96 spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in arm_get_spsr()
107 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, in arm_get_spsr()
111 return spsr; in arm_get_spsr()
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| /rk3399_ARM-atf/plat/intel/soc/stratix10/ |
| H A D | bl2_plat_setup.c | 146 uint32_t spsr; in get_spsr_for_bl33_entry() local
159 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in get_spsr_for_bl33_entry()
160 return spsr; in get_spsr_for_bl33_entry()
173 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); in bl2_plat_handle_post_image_load()
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| /rk3399_ARM-atf/plat/intel/soc/agilex/ |
| H A D | bl2_plat_setup.c | 159 uint32_t spsr; in get_spsr_for_bl33_entry() local
172 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in get_spsr_for_bl33_entry()
173 return spsr; in get_spsr_for_bl33_entry()
201 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); in bl2_plat_handle_post_image_load()
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| /rk3399_ARM-atf/plat/imx/imx8m/imx8mn/ |
| H A D | imx8mn_bl31_setup.c | 94 uint32_t spsr; in get_spsr_for_bl33_entry() local
102 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in get_spsr_for_bl33_entry()
103 return spsr; in get_spsr_for_bl33_entry()
157 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); in bl31_early_platform_setup2()
165 bl32_image_ep_info.spsr = 0; in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/plat/renesas/common/ |
| H A D | bl2_plat_mem_params_desc.c | 32 .ep_info.spsr = SPSR_64(MODE_EL3,
55 .ep_info.spsr = 0,
71 .ep_info.spsr = SPSR_64(BL33_MODE, MODE_SP_ELX,
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| /rk3399_ARM-atf/plat/qemu/common/ |
| H A D | qemu_bl2_setup.c | 207 uint32_t spsr; in qemu_get_spsr_for_bl33_entry() local
219 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in qemu_get_spsr_for_bl33_entry()
221 spsr = SPSR_MODE32(MODE32_svc, in qemu_get_spsr_for_bl33_entry()
225 return spsr; in qemu_get_spsr_for_bl33_entry()
314 if (GET_RW(bl_mem_params->ep_info.spsr) == MODE_RW_64) { in qemu_bl2_handle_post_image_load()
357 bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl32_entry(); in qemu_bl2_handle_post_image_load()
397 bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry(); in qemu_bl2_handle_post_image_load()
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| /rk3399_ARM-atf/plat/imx/imx8m/imx8mq/ |
| H A D | imx8mq_bl31_setup.c | 119 uint32_t spsr; in get_spsr_for_bl33_entry() local
127 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in get_spsr_for_bl33_entry()
128 return spsr; in get_spsr_for_bl33_entry()
181 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); in bl31_early_platform_setup2()
189 bl32_image_ep_info.spsr = 0; in bl31_early_platform_setup2()
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