1*c48d0aefSSumit Garg /*
2*c48d0aefSSumit Garg * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries.
3*c48d0aefSSumit Garg *
4*c48d0aefSSumit Garg * SPDX-License-Identifier: BSD-3-Clause
5*c48d0aefSSumit Garg */
6*c48d0aefSSumit Garg
7*c48d0aefSSumit Garg #include <assert.h>
8*c48d0aefSSumit Garg
9*c48d0aefSSumit Garg #include <arch.h>
10*c48d0aefSSumit Garg #include <common/desc_image_load.h>
11*c48d0aefSSumit Garg
12*c48d0aefSSumit Garg #include <platform_def.h>
13*c48d0aefSSumit Garg
14*c48d0aefSSumit Garg static struct bl_mem_params_node qti_image_descs[] = {
15*c48d0aefSSumit Garg {
16*c48d0aefSSumit Garg .image_id = BL31_IMAGE_ID,
17*c48d0aefSSumit Garg
18*c48d0aefSSumit Garg SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
19*c48d0aefSSumit Garg VERSION_2, image_info_t, 0),
20*c48d0aefSSumit Garg .image_info.image_base = BL31_BASE,
21*c48d0aefSSumit Garg .image_info.image_max_size = BL31_SIZE,
22*c48d0aefSSumit Garg
23*c48d0aefSSumit Garg SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
24*c48d0aefSSumit Garg VERSION_2, entry_point_info_t,
25*c48d0aefSSumit Garg SECURE | EXECUTABLE | EP_FIRST_EXE),
26*c48d0aefSSumit Garg .ep_info.pc = BL31_BASE,
27*c48d0aefSSumit Garg .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
28*c48d0aefSSumit Garg DISABLE_ALL_EXCEPTIONS),
29*c48d0aefSSumit Garg
30*c48d0aefSSumit Garg .next_handoff_image_id = BL32_IMAGE_ID,
31*c48d0aefSSumit Garg },
32*c48d0aefSSumit Garg {
33*c48d0aefSSumit Garg .image_id = BL32_IMAGE_ID,
34*c48d0aefSSumit Garg
35*c48d0aefSSumit Garg SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
36*c48d0aefSSumit Garg VERSION_2, image_info_t, 0),
37*c48d0aefSSumit Garg .image_info.image_base = BL32_BASE,
38*c48d0aefSSumit Garg .image_info.image_max_size = BL32_SIZE,
39*c48d0aefSSumit Garg
40*c48d0aefSSumit Garg SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
41*c48d0aefSSumit Garg VERSION_2, entry_point_info_t,
42*c48d0aefSSumit Garg SECURE | EXECUTABLE),
43*c48d0aefSSumit Garg .ep_info.pc = BL32_BASE,
44*c48d0aefSSumit Garg .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
45*c48d0aefSSumit Garg DISABLE_ALL_EXCEPTIONS),
46*c48d0aefSSumit Garg
47*c48d0aefSSumit Garg .next_handoff_image_id = BL33_IMAGE_ID,
48*c48d0aefSSumit Garg },
49*c48d0aefSSumit Garg {
50*c48d0aefSSumit Garg .image_id = BL33_IMAGE_ID,
51*c48d0aefSSumit Garg
52*c48d0aefSSumit Garg SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
53*c48d0aefSSumit Garg VERSION_2, image_info_t, 0),
54*c48d0aefSSumit Garg .image_info.image_base = BL33_BASE,
55*c48d0aefSSumit Garg .image_info.image_max_size = BL33_SIZE,
56*c48d0aefSSumit Garg
57*c48d0aefSSumit Garg SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
58*c48d0aefSSumit Garg VERSION_2, entry_point_info_t,
59*c48d0aefSSumit Garg NON_SECURE | EXECUTABLE),
60*c48d0aefSSumit Garg .ep_info.pc = BL33_BASE,
61*c48d0aefSSumit Garg .ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
62*c48d0aefSSumit Garg DISABLE_ALL_EXCEPTIONS),
63*c48d0aefSSumit Garg
64*c48d0aefSSumit Garg .next_handoff_image_id = INVALID_IMAGE_ID,
65*c48d0aefSSumit Garg },
66*c48d0aefSSumit Garg };
REGISTER_BL_IMAGE_DESCS(qti_image_descs)67*c48d0aefSSumit Garg REGISTER_BL_IMAGE_DESCS(qti_image_descs)
68*c48d0aefSSumit Garg
69*c48d0aefSSumit Garg struct image_info *qti_get_image_info(unsigned int image_id)
70*c48d0aefSSumit Garg {
71*c48d0aefSSumit Garg struct bl_mem_params_node *desc;
72*c48d0aefSSumit Garg
73*c48d0aefSSumit Garg desc = get_bl_mem_params_node(image_id);
74*c48d0aefSSumit Garg assert(desc);
75*c48d0aefSSumit Garg return &desc->image_info;
76*c48d0aefSSumit Garg }
77