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/rk3399_ARM-atf/fdts/
H A Dstm32mp251.dtsi27 clocks {
96 clocks = <&rcc CK_KER_USART2>;
104 clocks = <&rcc CK_KER_USART3>;
112 clocks = <&rcc CK_KER_UART4>;
120 clocks = <&rcc CK_KER_UART5>;
128 clocks = <&rcc CK_KER_I2C1>;
136 clocks = <&rcc CK_KER_I2C2>;
144 clocks = <&rcc CK_KER_I2C3>;
152 clocks = <&rcc CK_KER_I2C4>;
160 clocks = <&rcc CK_KER_I2C5>;
[all …]
H A Dstm32mp151.dtsi40 clocks {
84 clocks = <&rcc TIM12_K>;
93 clocks = <&rcc USART2_K>;
102 clocks = <&rcc USART3_K>;
111 clocks = <&rcc UART4_K>;
121 clocks = <&rcc UART5_K>;
132 clocks = <&rcc I2C2_K>;
145 clocks = <&rcc UART7_K>;
154 clocks = <&rcc UART8_K>;
163 clocks = <&rcc USART6_K>;
[all …]
H A Dstm32mp131.dtsi22 clocks = <&rcc CK_MPU>;
29 clocks {
85 clocks = <&rcc USART3_K>;
94 clocks = <&rcc UART4_K>;
103 clocks = <&rcc UART5_K>;
112 clocks = <&rcc UART7_K>;
121 clocks = <&rcc UART8_K>;
130 clocks = <&rcc USART6_K>;
138 clocks = <&rcc USBO_K>;
155 clocks = <&rcc USART1_K>;
[all …]
H A Dmorello-coresight.dtsi19 clocks = <&soc_refclk50mhz>;
27 clocks = <&soc_refclk50mhz>;
42 clocks = <&soc_refclk50mhz>;
50 clocks = <&soc_refclk50mhz>;
65 clocks = <&soc_refclk50mhz>;
73 clocks = <&soc_refclk50mhz>;
88 clocks = <&soc_refclk50mhz>;
96 clocks = <&soc_refclk50mhz>;
164 clocks = <&soc_refclk50mhz>;
178 clocks = <&soc_refclk50mhz>;
[all …]
H A Drtsm_ve-motherboard.dtsi127 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
131 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
139 clocks = <&v2m_clk24mhz>;
151 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
159 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
167 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
175 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
183 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
191 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
199 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
[all …]
H A Dtc-base.dtsi33 /* Use SCMI controlled clocks */
36 clocks = <&scmi_clk 0>; \
40 clocks = <&scmi_clk 1>; \
44 clocks = <&scmi_clk 2>; \
46 /* Use fixed clocks */
49 clocks = <&dpu_aclk>; \
53 clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \
132 clocks = <&scmi_dvfs 0>;
142 clocks = <&scmi_dvfs 0>;
168 clocks = <&scmi_dvfs 1>;
[all …]
H A Dmorello-fvp.dts81 clocks = <&scmi_dvfs 0>;
89 clocks = <&scmi_dvfs 0>;
97 clocks = <&scmi_dvfs 1>;
105 clocks = <&scmi_dvfs 1>;
157 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
165 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
H A Dstm32mp13xf.dtsi13 clocks = <&rcc SAES_K>;
21 clocks = <&rcc PKA>;
H A Dstm32mp13xc.dtsi14 clocks = <&rcc SAES_K>;
22 clocks = <&rcc PKA>;
H A Dcorstone700.dtsi78 clocks = <&uartclk>, <&refclk100mhz>;
87 clocks = <&uartclk>, <&refclk100mhz>;
117 clocks = <&refclk100mhz>;
129 clocks = <&refclk100mhz>;
141 clocks = <&refclk100mhz>;
H A Dtc-fvp.dtsi58 clocks = <&soc_refclk>;
66 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
74 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
H A Dmorello-soc.dts63 clocks = <&scmi_dvfs 0>;
80 clocks = <&scmi_dvfs 0>;
97 clocks = <&scmi_dvfs 1>;
114 clocks = <&scmi_dvfs 1>;
230 clocks = <&dpu_aclk>;
237 clocks = <&scmi_clk 1>;
261 clocks = <&dpu_aclk>;
296 clocks = <&clk_gpu>;
430 clocks = <&soc_refclk85mhz>, <&i2s_audclk>, <&soc_refclk85mhz>;
440 clocks = <&i2s_audclk>;
H A Da5ds.dts92 clocks = <&refclk24mhz>;
112 clocks = <&refclk7500khz>;
121 clocks = <&refclk7500khz>;
H A Dn1sdp-single-chip.dts51 clocks = <&soc_hdlcdclk>;
68 clocks = <&soc_refclk60mhz>;
H A Dstm32mp153.dtsi15 clocks = <&rcc CK_MPU>;
H A Dstm32mp15xc.dtsi13 clocks = <&rcc CRYP1>;
H A Dmorello.dtsi61 clocks = <&soc_refclk50mhz>;
109 clocks = <&soc_uartclk>, <&soc_refclk50mhz>;
H A Drdaspen.dts113 clocks = <&soc_clk24mhz>, <&soc_clk24mhz>;
128 clocks = <&soc_clk24mhz>;
H A Dstm32mp153c-lxa-fairytux2.dts84 /* change parent clocks */
H A Dstm32mp157c-lxa-tac.dts84 /* change parent clocks */
H A Darm_fpga.dts85 clocks = <&uartclk>, <&bus_refclk>;
H A Drd1ae.dts326 clocks = <&soc_clk24mhz>, <&soc_clk24mhz>;
341 clocks = <&soc_clk24mhz>;
417 clocks = <&soc_clk24mhz>, <&soc_clk24mhz>;
H A Dfvp-ve-Cortex-A5x1.dts55 clocks = <&oscclk3>;
H A Dn1sdp.dtsi205 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dpm_api_clock.c828 static struct pm_clock clocks[] = { variable
2471 (void)memcpy(name, clocks[clock_id_num].name, CLK_NAME_LEN); in pm_api_clock_get_name()
2512 clock_nodes = *clocks[clock_id].nodes; in pm_api_clock_get_topology()
2513 num_nodes = clocks[clock_id].num_nodes; in pm_api_clock_get_topology()
2573 clock_nodes = *clocks[clock_id].nodes; in pm_api_clock_get_fixedfactor_params()
2574 num_nodes = clocks[clock_id].num_nodes; in pm_api_clock_get_fixedfactor_params()
2629 clk_parents = *clocks[clock_id].parents; in pm_api_clock_get_parents()
2712 nodes = *clocks[clock_id].nodes; in pm_api_clock_get_max_divisor()
2713 for (i = 0; i < clocks[clock_id].num_nodes; i++) { in pm_api_clock_get_max_divisor()
3133 nodes = *clocks[clock_id].nodes; in pm_clock_has_div()
[all …]

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