| /rk3399_ARM-atf/bl32/tsp/ |
| H A D | tsp_private.h | 54 uint64_t arg3,
62 uint64_t arg3,
70 uint64_t arg3,
79 uint64_t arg3,
109 uint64_t arg3,
118 uint64_t arg3,
127 uint64_t arg3,
136 uint64_t arg3,
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| H A D | tsp_common.c | 37 uint64_t arg3, in set_smc_args() argument
55 write_sp_arg(pcpu_smc_args, SMC_ARG3, arg3); in set_smc_args()
68 u_register_t arg3) in tsp_setup() argument
74 tsp_early_platform_setup(arg0, arg1, arg2, arg3); in tsp_setup()
87 uint64_t arg3, in tsp_system_off_main() argument
115 uint64_t arg3, in tsp_system_reset_main() argument
145 uint64_t arg3, in tsp_abort_smc_handler() argument
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| H A D | tsp_ffa_main.c | 86 uint64_t arg3, in ffa_test_relay() argument
283 uint64_t arg3, in tsp_cpu_off_main() argument
321 uint64_t arg3, in tsp_cpu_suspend_main() argument
358 uint64_t arg3, in tsp_cpu_resume_main() argument
391 uint64_t arg3, in handle_framework_message() argument
405 if (arg3 == PSCI_CPU_OFF) { in handle_framework_message()
406 return tsp_cpu_off_main(arg0, arg1, arg2, arg3, in handle_framework_message()
408 } else if (arg3 == PSCI_CPU_SUSPEND_AARCH64) { in handle_framework_message()
409 return tsp_cpu_suspend_main(arg0, arg1, arg2, arg3, in handle_framework_message()
414 if (arg3 == FFA_WB_TYPE_NOTS2RAM) { in handle_framework_message()
[all …]
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| /rk3399_ARM-atf/plat/xilinx/common/include/ |
| H A D | pm_api_sys.h | 72 #define PM_PACK_PAYLOAD4(pl, mid, flag, arg0, arg1, arg2, arg3) { \ argument
73 pl[3] = (uint32_t)(arg3); \
77 #define PM_PACK_PAYLOAD5(pl, mid, flag, arg0, arg1, arg2, arg3, arg4) { \ argument
79 PM_PACK_PAYLOAD4(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3)); \
82 #define PM_PACK_PAYLOAD6(pl, mid, flag, arg0, arg1, arg2, arg3, arg4, arg5) { \ argument
84 PM_PACK_PAYLOAD5(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3), (arg4)); \
87 #define PM_PACK_PAYLOAD7(pl, mid, flag, arg0, arg1, arg2, arg3, arg4, arg5, arg6) { \ argument
89 PM_PACK_PAYLOAD6(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3), (arg4), (arg5)); \
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| /rk3399_ARM-atf/plat/arm/common/tsp/ |
| H A D | arm_tsp_setup.c | 46 u_register_t arg2, u_register_t arg3) in arm_tsp_early_platform_setup() argument
49 secure_tl = (struct transfer_list_header *)arg3; in arm_tsp_early_platform_setup()
76 u_register_t arg2, u_register_t arg3) in tsp_early_platform_setup() argument
78 arm_tsp_early_platform_setup(arg0, arg1, arg2, arg3); in tsp_early_platform_setup()
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| /rk3399_ARM-atf/plat/arm/common/sp_min/ |
| H A D | arm_sp_min_setup.c | 80 u_register_t arg2, u_register_t arg3) in arm_sp_min_early_platform_setup() argument
88 secure_tl = (struct transfer_list_header *)arg3; in arm_sp_min_early_platform_setup()
158 u_register_t arg2, u_register_t arg3) in plat_arm_sp_min_early_platform_setup() argument
160 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in plat_arm_sp_min_early_platform_setup()
182 u_register_t arg2, u_register_t arg3) in sp_min_early_platform_setup2() argument
184 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in sp_min_early_platform_setup2()
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| /rk3399_ARM-atf/plat/arm/board/fvp/tsp/ |
| H A D | fvp_tsp_setup.c | 12 u_register_t arg2, u_register_t arg3) in tsp_early_platform_setup() argument
14 arm_tsp_early_platform_setup(arg0, arg1, arg2, arg3); in tsp_early_platform_setup()
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| /rk3399_ARM-atf/plat/arm/board/corstone700/sp_min/ |
| H A D | corstone700_sp_min_setup.c | 10 u_register_t arg2, u_register_t arg3) in plat_arm_sp_min_early_platform_setup() argument
12 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in plat_arm_sp_min_early_platform_setup()
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| /rk3399_ARM-atf/plat/arm/board/fvp_ve/sp_min/ |
| H A D | fvp_ve_sp_min_setup.c | 12 u_register_t arg2, u_register_t arg3) in plat_arm_sp_min_early_platform_setup() argument
14 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in plat_arm_sp_min_early_platform_setup()
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| /rk3399_ARM-atf/include/plat/marvell/odyssey/csr/ |
| H A D | ody-csr-plat.h | 24 #define __ody_csr_fatal(name, num_args, arg1, arg2, arg3, arg4, arg5, arg6) { BUG_ON(0); return 0; } argument
31 #define __ody_csr_fatal(name, num_args, arg1, arg2, arg3, arg4, arg5, arg6) { assert(0); return 0; } argument
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| /rk3399_ARM-atf/plat/arm/board/fvp_ve/ |
| H A D | fvp_ve_bl2_setup.c | 16 …2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) in bl2_early_platform_setup2() argument
18 arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3); in bl2_early_platform_setup2()
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| /rk3399_ARM-atf/plat/brcm/common/ |
| H A D | brcm_bl31_setup.c | 136 bl33_image_ep_info.args.arg3 = 0U; in brcm_bl31_early_platform_setup()
184 bl33_image_ep_info.args.arg3 = 0ULL; in brcm_bl31_early_platform_setup()
189 u_register_t arg2, u_register_t arg3) in bl31_early_platform_setup2() argument
195 brcm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in bl31_early_platform_setup2()
197 plat_bcm_bl31_early_platform_setup((void *)arg0, (void *)arg3); in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/plat/arm/common/ |
| H A D | arm_bl31_setup.c | 174 u_register_t arg2, u_register_t arg3) in arm_bl31_early_platform_setup() argument
192 bl33_image_ep_info.args.arg3 = FW_NS_HANDOFF_BASE; in arm_bl31_early_platform_setup()
197 secure_tl = (struct transfer_list_header *)arg3; in arm_bl31_early_platform_setup()
233 (void)arg3; in arm_bl31_early_platform_setup()
278 assert(((uintptr_t)arg3) == ARM_BL31_PLAT_PARAM_VAL); in arm_bl31_early_platform_setup()
310 bl32_image_ep_info.args.arg3 = in arm_bl31_early_platform_setup()
351 bl33_image_ep_info.args.arg3 = 0U; in arm_bl31_early_platform_setup()
358 u_register_t arg2, u_register_t arg3) in bl31_early_platform_setup2() argument
363 arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3); in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/plat/rpi/rpi3/ |
| H A D | rpi3_bl31_setup.c | 75 u_register_t arg2, u_register_t arg3) in bl31_early_platform_setup2() argument
120 if (transfer_list_check_header((void *)arg3) == TL_OPS_NON) { in bl31_early_platform_setup2()
129 bl31_tl = (void *)arg3; /* saved TL address from BL2 */ in bl31_early_platform_setup2()
155 bl33_image_ep_info.args.arg3 = 0ULL; in bl31_early_platform_setup2()
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| H A D | rpi3_bl2_setup.c | 69 u_register_t arg2, u_register_t arg3) in bl2_early_platform_setup2() argument
92 bl2_tl = (struct transfer_list_header *)(uintptr_t)arg3; in bl2_early_platform_setup2()
107 event_log_size = arg3; in bl2_early_platform_setup2()
173 bl_mem_params->ep_info.args.arg3 = (uintptr_t)bl2_tl; in bl2_plat_handle_post_image_load()
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| /rk3399_ARM-atf/plat/mediatek/drivers/dfd/ |
| H A D | dfd.c | 14 u_register_t arg2, u_register_t arg3, in dfd_smc_dispatcher() argument
22 dfd_setup(arg1, arg2, arg3); in dfd_smc_dispatcher()
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| /rk3399_ARM-atf/lib/debugfs/ |
| H A D | debugfs_smc.c | 67 u_register_t arg3, in debugfs_smc_handler() argument
90 arg3 &= 0xffffffff; in debugfs_smc_handler()
150 ret = read(arg2, DEBUGFS_SHARED_BUF_VIRT, arg3); in debugfs_smc_handler()
158 ret = seek(arg2, arg3, arg4); in debugfs_smc_handler()
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| /rk3399_ARM-atf/drivers/arm/css/scmi/ |
| H A D | scmi_private.h | 105 #define SCMI_PAYLOAD_ARG3(payld_arr, arg1, arg2, arg3) do { \ argument
107 mmio_write_32((uintptr_t)&payld_arr[2], arg3); \
110 #define SCMI_PAYLOAD_ARG4(payld_arr, arg1, arg2, arg3, arg4) do { \ argument
111 SCMI_PAYLOAD_ARG3(payld_arr, arg1, arg2, arg3); \
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| /rk3399_ARM-atf/plat/arm/css/common/ |
| H A D | css_bl2_setup.c | 57 u_register_t arg2, u_register_t arg3) in bl2_early_platform_setup2() argument
59 arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3); in bl2_early_platform_setup2()
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| /rk3399_ARM-atf/plat/arm/board/juno/ |
| H A D | juno_bl31_setup.c | 17 u_register_t arg1, u_register_t arg2, u_register_t arg3) in bl31_early_platform_setup2() argument
36 arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3); in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/plat/arm/board/fvp/sp_min/ |
| H A D | fvp_sp_min_setup.c | 20 u_register_t arg2, u_register_t arg3) in plat_arm_sp_min_early_platform_setup() argument
39 tl = (struct transfer_list_header *)arg3; in plat_arm_sp_min_early_platform_setup()
56 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in plat_arm_sp_min_early_platform_setup()
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| /rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/ |
| H A D | zynqmp_pm_api_sys.h | 55 #define PM_PACK_PAYLOAD4(pl, flag, arg0, arg1, arg2, arg3) { \ argument
56 pl[3] = (uint32_t)(arg3); \
60 #define PM_PACK_PAYLOAD5(pl, flag, arg0, arg1, arg2, arg3, arg4) { \ argument
62 PM_PACK_PAYLOAD4(pl, (flag), (arg0), (arg1), (arg2), (arg3)); \
65 #define PM_PACK_PAYLOAD6(pl, flag, arg0, arg1, arg2, arg3, arg4, arg5) { \ argument
67 PM_PACK_PAYLOAD5(pl, (flag), (arg0), (arg1), (arg2), (arg3), (arg4)); \
161 uint32_t arg3, uint32_t *data, uint32_t flag);
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| /rk3399_ARM-atf/services/spd/opteed/ |
| H A D | opteed_common.c | 24 uint64_t arg1, uint64_t arg2, uint64_t arg3, in opteed_init_optee_ep_state() argument
63 optee_entry_point->args.arg3 = arg3; in opteed_init_optee_ep_state()
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| /rk3399_ARM-atf/plat/imx/imx93/ |
| H A D | imx93_bl31_setup.c | 60 u_register_t arg2, u_register_t arg3) in bl31_early_platform_setup2() argument
91 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; in bl31_early_platform_setup2()
92 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/plat/nuvoton/npcm845x/ |
| H A D | npcm845x_bl31_setup.c | 135 u_register_t arg2, u_register_t arg3) in bl31_early_platform_setup2() argument
137 arg0 = arg1 = arg2 = arg3 = 0; in bl31_early_platform_setup2()
140 void *plat_params_from_bl2 = (void *)arg3; in bl31_early_platform_setup2()
221 bl33_image_ep_info.args.arg3 = 0U; in bl31_early_platform_setup2()
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