Searched refs:PLATFORM_MODEL (Results 1 – 19 of 19) sorted by relevance
20 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX532 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX558 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in socfpga_pwr_domain_on()70 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 in socfpga_pwr_domain_on()81 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in socfpga_pwr_domain_on()123 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 in socfpga_pwr_domain_suspend()131 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 in socfpga_pwr_domain_suspend()171 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 in socfpga_pwr_domain_suspend_finish()179 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 in socfpga_pwr_domain_suspend_finish()211 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in socfpga_system_reset()[all …]
14 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX16 #elif PLATFORM_MODEL == PLAT_SOCFPGA_N5X18 #elif PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
20 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 in plat_flush_next_bl_params()
164 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in socfpga_io_setup()
35 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5232 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in intel_fpga_config_start()257 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in intel_fpga_config_start()342 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in intel_fpga_config_write()374 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5389 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5791 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX52458 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX52491 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
23 #if ((PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10) || \ in enable_ns_peripheral_access()24 (PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX) || \ in enable_ns_peripheral_access()25 (PLATFORM_MODEL == PLAT_SOCFPGA_N5X)) in enable_ns_peripheral_access()94 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in enable_ns_peripheral_access()100 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in enable_ns_peripheral_access()111 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 in enable_ns_peripheral_access()
79 #if (PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX) || (PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5) in deassert_peripheral_reset()114 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5166 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 in socfpga_f2s_bridge_mask()197 #elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in socfpga_f2s_bridge_mask()403 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in socfpga_bridges_enable()411 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in socfpga_bridges_enable()603 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in socfpga_bridges_enable()901 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in socfpga_bridges_disable()1010 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in socfpga_bridges_disable()1194 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 in socfpga_bridges_disable()
59 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in socfpga_get_handoff()
39 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX557 #if ((PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10) || \58 (PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX) || \59 (PLATFORM_MODEL == PLAT_SOCFPGA_N5X))92 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5101 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5145 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
35 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX541 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5172 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10176 #elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
56 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX1092 #elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX126 #elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5172 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
46 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
13 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5285 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
16 #define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10 macro
17 #define PLATFORM_MODEL PLAT_SOCFPGA_N5X macro
17 #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX macro
40 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5612 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5655 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
18 #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5 macro
629 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in intel_fcs_encryption_ext()705 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in intel_fcs_decryption_ext()1278 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in intel_fcs_get_digest_update_finalize()1517 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in intel_fcs_mac_verify_update_finalize()2014 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in intel_fcs_ecdsa_sha2_data_sign_update_finalize()2249 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize()2656 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in intel_fcs_aes_crypt_init()2740 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in intel_fcs_aes_crypt_update_finalize()2812 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in intel_fcs_aes_crypt_update_finalize()2827 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 in intel_fcs_aes_crypt_update_finalize()