Merge changes I1dfb95aa,I9eb61c48 into integration

* changes:
feat(intel): support FCS commands with SiPSVC V3 framework
feat(intel): implementation of SiPSVC-V3 protocol framework

feat(intel): implementation of SiPSVC-V3 protocol framework

- Develop SiPSVC-V3 framework to support async/yielding SMC calls.
- Add support for multi clients with multiple jobs running together.
-

feat(intel): implementation of SiPSVC-V3 protocol framework

- Develop SiPSVC-V3 framework to support async/yielding SMC calls.
- Add support for multi clients with multiple jobs running together.
- Add support for SDM doorbell interrupt handling.
- Keep the framework backward compatible with V1 clients.
- Enable the framework on all the platform Agilex7, Agilex5, N5X,
and Stratix10.

Change-Id: I9eb61c48be89867b4227e084493bfcf67cbe7924
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@altera.com>

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Merge "fix(intel): update warm reset routine and bootscratch register usage" into integration

fix(intel): update warm reset routine and bootscratch register usage

Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bit

fix(intel): update warm reset routine and bootscratch register usage

Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bits to
determine the warm reset and SMP boot requests.
Also handle the unaligned DEVICE/IO memory store and load
in the assembly entrypoint startup code.

Agilex, Stratix10, N5X platforms:
Use only the LSB 4bits [3:0] of the boot scratch COLD6 register
to detect the warm reset request.

Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "feat(intel): add build option for boot source" into integration

Merge "fix(intel): update Agilex5 warm reset subroutines" into integration

fix(intel): update Agilex5 warm reset subroutines

Update the 'plat_get_my_entrypoint' assembly routine to
differentiate between cold reset, warm reset and SMP
secondary boot cores request.
Add secon

fix(intel): update Agilex5 warm reset subroutines

Update the 'plat_get_my_entrypoint' assembly routine to
differentiate between cold reset, warm reset and SMP
secondary boot cores request.
Add secondary core boot request markup in BL31.
Perform CACHE flush/clean ops in case of warm reset request also.

Change-Id: I7d33e362a3a513c60c8333e062ce832aa7facf38
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): add build option for boot source

Existing boot source is hardcoded in socfpga_plat_def.h.
To change boot source, user need to update code.
Thus adding this will remove the code update n

feat(intel): add build option for boot source

Existing boot source is hardcoded in socfpga_plat_def.h.
To change boot source, user need to update code.
Thus adding this will remove the code update needed when
need to change boot source.

Also, it will have ARM_LINUX_KERNEL_AS_BL33 flag for each
platform in platform.mk. This will be easily to control
based on platform build.

Change-Id: I383beb8cbca5ec0f247221ad42796554adc3daae
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "fix(intel): update all the platforms hand-off data offset value" into integration

fix(intel): update all the platforms hand-off data offset value

Move the hand-off data offset value from the common
platform header file to each socfpga platform specific
header file.

Change-Id: Ic

fix(intel): update all the platforms hand-off data offset value

Move the hand-off data offset value from the common
platform header file to each socfpga platform specific
header file.

Change-Id: Icfe917f788814c329659c44e298cf05d6e3d0dd9
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "feat(intel): direct boot from TF-A to Linux for Agilex" into integration

feat(intel): direct boot from TF-A to Linux for Agilex

Enable and update code for TF-A direct boot Linux
for Agilex platform.

Change-Id: Id95986b7015a2a01f0aff80e1c7d8f8bb8fb4637
Signed-off-by: Sie

feat(intel): direct boot from TF-A to Linux for Agilex

Enable and update code for TF-A direct boot Linux
for Agilex platform.

Change-Id: Id95986b7015a2a01f0aff80e1c7d8f8bb8fb4637
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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Merge changes Iaa189c54,I8856b495 into integration

* changes:
feat(intel): enable query of fip offset on RSU
feat(intel): support query of fip offset using RSU

feat(intel): enable query of fip offset on RSU

Enable query of fip offset from QSPI on RSU boot for
Intel agilex and intel agilex5 platform

Change-Id: Iaa189c54723a8656b9691da5849fd86b9986cfa1
Sign

feat(intel): enable query of fip offset on RSU

Enable query of fip offset from QSPI on RSU boot for
Intel agilex and intel agilex5 platform

Change-Id: Iaa189c54723a8656b9691da5849fd86b9986cfa1
Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>

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Merge changes from topic "agilex5" into integration

* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for A

Merge changes from topic "agilex5" into integration

* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for Agilex5 SoC FPGA
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
feat(intel): ddr driver for Agilex5 SoC FPGA
feat(intel): power manager for Agilex5 SoC FPGA
feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA
feat(intel): reset manager support for Agilex5 SoC FPGA
feat(intel): mailbox and SMC support for Agilex5 SoC FPGA
feat(intel): system manager support for Agilex5 SoC FPGA
feat(intel): memory controller support for Agilex5 SoC FPGA
feat(intel): clock manager support for Agilex5 SoC FPGA
feat(intel): mmc support for Agilex5 SoC FPGA
feat(intel): uart support for Agilex5 SoC FPGA
feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA

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feat(intel): platform enablement for Agilex5 SoC FPGA

This patch is used to enable platform enablement for
Agilex5 SoC FPGA.

New feature:
1. Added ATF->Zephyr boot option
2. Added xlat_v2 for MMU

feat(intel): platform enablement for Agilex5 SoC FPGA

This patch is used to enable platform enablement for
Agilex5 SoC FPGA.

New feature:
1. Added ATF->Zephyr boot option
2. Added xlat_v2 for MMU
3. Added ATF->Linux boot option
4. Added SMP support
5. Added HPS bridges support
6. Added EMULATOR support
7. Added DDR support
8. Added GICv3 Redistirbution init
9. Added SDMMC/NAND/Combo Phy support
10. Updated GIC as secure access
11. Added CCU driver support
12. Updated product name -> Agilex5
13. Updated register address based on y22ww52.2 RTL
14. Updated system counter freq to 400MHz

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ice82f3e4535527cfd01500d4d528402985f72009

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Merge changes I38545567,I2f52d3ea into integration

* changes:
feat(intel): restructure sys mgr for S10/N5X
feat(intel): restructure sys mgr for Agilex

feat(intel): restructure sys mgr for Agilex

This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for t

feat(intel): restructure sys mgr for Agilex

This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for those common declaration only.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I2f52d3eaf47716f7dfc636bbf1a23d68a04f39cb

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Merge changes I43a9d83c,Ibfaa47fb into integration

* changes:
fix(intel): fix Agilex and N5X clock manager to main PLL C0
feat(intel): implement timer init divider via CPU frequency for N5X

fix(intel): fix Agilex and N5X clock manager to main PLL C0

Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ

fix(intel): fix Agilex and N5X clock manager to main PLL C0

Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ to
PLAT_HZ_CONVERT_TO_MHZ.
2. Updated get_cpu_clk to point to get_mpu_clk and added comment.
3. Added get_mpu_clk to get clock from main PLL C0 and Peri PLL C0.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I43a9d83caa832b61eba93a830e2a671fd4dffa19

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Merge "fix(intel): fix UART baud rate and clock" into integration

fix(intel): fix UART baud rate and clock

Revise the UART baud rate and clock for general platform build,
SIMIC build and EMU build.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id:

fix(intel): fix UART baud rate and clock

Revise the UART baud rate and clock for general platform build,
SIMIC build and EMU build.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I62fefe7b96d5124e75d2810b4fbc1640422b1353

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Merge "feat(intel): implement timer init divider via cpu frequency. (#1)" into integration

feat(intel): implement timer init divider via cpu frequency. (#1)

Get cpu frequency and update the timer init div with it.
The timer is vary based on the cpu frequency instead of hardcoded.
The impl

feat(intel): implement timer init divider via cpu frequency. (#1)

Get cpu frequency and update the timer init div with it.
The timer is vary based on the cpu frequency instead of hardcoded.
The implementation shall apply to only Agilex and S10

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I61684d9762ad34e5a60b8b176b60c8848db4b422

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Merge changes Iccfa7ec6,Ide9a7af4 into integration

* changes:
feat(intel): add macro to switch between different UART PORT
feat(intel): add SMC support for ROM Patch SHA384 mailbox