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Searched refs:GENMASK (Results 1 – 25 of 85) sorted by relevance

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/rk3399_ARM-atf/plat/intel/soc/n5x/include/
H A Dn5x_clock_manager.h15 #define CLKMGR_PLLGLOB_VCO_PSRC_MASK GENMASK(17, 16)
17 #define CLKMGR_PLLDIV_FDIV_MASK GENMASK(16, 8)
19 #define CLKMGR_PLLDIV_REFCLKDIV_MASK GENMASK(5, 0)
21 #define CLKMGR_PLLDIV_OUTDIV_QDIV_MASK GENMASK(26, 24)
24 #define CLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0)
26 #define CLKMGR_PLLOUTDIV_C1CNT_MASK GENMASK(12, 8)
28 #define CLKMGR_PLLDIV_OUTDIV_QDIV_MASK GENMASK(26, 24)
30 #define CLKMGR_CLKSRC_MASK GENMASK(18, 16)
32 #define CLKMGR_NOCDIV_DIVIDER_MASK GENMASK(1, 0)
/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp13_rcc.h246 #define RCC_MP_APRSTCR_RSTTO_MASK GENMASK(14, 8)
250 #define RCC_MP_APRSTSR_RSTTOV_MASK GENMASK(14, 8)
254 #define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0)
344 #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
348 #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
363 #define RCC_RDLSICR_MRD_MASK GENMASK(20, 16)
365 #define RCC_RDLSICR_EADLY_MASK GENMASK(26, 24)
367 #define RCC_RDLSICR_SPARE_MASK GENMASK(31, 27)
411 #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
413 #define RCC_HSICFGR_HSITRIM_MASK GENMASK(14, 8)
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H A Dstm32_uart_regs.h43 #define USART_CR1_DEDT GENMASK(20, 16)
49 #define USART_CR1_DEAT GENMASK(25, 21)
72 #define USART_CR2_STOP GENMASK(13, 12)
82 #define USART_CR2_ABRMODE GENMASK(22, 21)
86 #define USART_CR2_ADD GENMASK(31, 24)
105 #define USART_CR3_SCARCNT GENMASK(19, 17)
109 #define USART_CR3_WUS GENMASK(21, 20)
115 #define USART_CR3_RXFTCFG GENMASK(27, 25)
120 #define USART_CR3_TXFTCFG GENMASK(31, 29)
126 #define USART_BRR_DIV_FRACTION GENMASK(3, 0)
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H A Dstm32mp15_rcc.h263 #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
265 #define RCC_HSICFGR_HSITRIM_MASK GENMASK(14, 8)
267 #define RCC_HSICFGR_HSICAL_MASK GENMASK(24, 16)
269 #define RCC_HSICFGR_HSICAL_TEMP_MASK GENMASK(27, 25)
272 #define RCC_CSICFGR_CSITRIM_MASK GENMASK(12, 8)
274 #define RCC_CSICFGR_CSICAL_MASK GENMASK(23, 16)
282 #define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0)
290 #define RCC_ASSCKSELR_AXISSRC_MASK GENMASK(2, 0)
295 #define RCC_RCK12SELR_PLL12SRC_MASK GENMASK(1, 0)
300 #define RCC_MPCKDIVR_MPUDIV_MASK GENMASK(2, 0)
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H A Dstm32_i2c.h23 #define I2C_CR1_DNF GENMASK(11, 8)
38 #define I2C_CR2_SADD GENMASK(9, 0)
46 #define I2C_CR2_NBYTES GENMASK(23, 16)
53 #define I2C_OAR1_OA1 GENMASK(9, 0)
58 #define I2C_OAR2_OA2 GENMASK(7, 1)
59 #define I2C_OAR2_OA2MSK GENMASK(10, 8)
63 #define I2C_OAR2_OA2MASK03 GENMASK(9, 8)
67 #define I2C_OAR2_OA2MASK07 GENMASK(10, 8)
71 #define I2C_TIMINGR_SCLL GENMASK(7, 0)
72 #define I2C_TIMINGR_SCLH GENMASK(15, 8)
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H A Dstm32mp1_ddr_regs.h139 #define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7)
143 #define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25)
158 #define DDRPHYC_PTR0_TDLLSRST_MASK GENMASK(5, 0)
160 #define DDRPHYC_PTR0_TDLLLOCK_MASK GENMASK(17, 6)
162 #define DDRPHYC_PTR0_TITMSRST_MASK GENMASK(21, 18)
166 #define DDRPHYC_ACIOCR_CKPDD_MASK GENMASK(10, 8)
168 #define DDRPHYC_ACIOCR_CKPDR_MASK GENMASK(13, 11)
170 #define DDRPHYC_ACIOCR_CSPDD_MASK GENMASK(21, 18)
178 #define DDRPHYC_DSGCR_CKEPDD_MASK GENMASK(19, 16)
180 #define DDRPHYC_DSGCR_ODTPDD_MASK GENMASK(23, 20)
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H A Dbsec2_reg.h15 #define DATA_LOWER_OTP_PERLOCK_MASK GENMASK(2, 0)
18 #define DATA_UPPER_OTP_PERLOCK_MASK GENMASK(3, 0)
62 #define BSEC_CONF_FRQ_MASK GENMASK(2, 1)
64 #define BSEC_CONF_PRG_WIDTH_MASK GENMASK(6, 3)
66 #define BSEC_CONF_TREAD_MASK GENMASK(8, 7)
96 #define BSEC_FEN_ALL_MSK GENMASK(14, 0)
99 #define BSEC_IPVR_MSK GENMASK(7, 0)
H A Dstm32mp_ddrctrl_regs.h197 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
203 #define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0)
206 #define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4)
209 #define DDRCTRL_STAT_SELFREF_STATE_MASK GENMASK(9, 8)
218 #define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12)
229 #define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16)
237 #define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_MASK GENMASK(27, 16)
240 #define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16)
243 #define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK GENMASK(31, 30)
250 #define DDRCTRL_DFIMISC_DFI_FREQUENCY GENMASK(12, 8)
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H A Dstm32mp_risab_regs.h219 #define RISAB_IAESR_IACID_MASK GENMASK(2, 0)
246 #define RISAB_PGx_CIDCFGR_DCCID_MASK GENMASK(6, 4)
250 #define RISAB_HWCFGR1_CFG1_MASK GENMASK(3, 0)
252 #define RISAB_HWCFGR1_CFG2_MASK GENMASK(7, 4)
254 #define RISAB_HWCFGR1_CFG3_MASK GENMASK(11, 8)
256 #define RISAB_HWCFGR1_CFG4_MASK GENMASK(15, 12)
258 #define RISAB_HWCFGR1_CFG5_MASK GENMASK(19, 16)
260 #define RISAB_HWCFGR1_CFG6_MASK GENMASK(23, 20)
262 #define RISAB_HWCFGR1_CFG7_MASK GENMASK(27, 24)
266 #define RISAB_VERR_MINREV_MASK GENMASK(3, 0)
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H A Dstpmic1.h89 #define LDO_VOLTAGE_MASK GENMASK(6, 2)
90 #define BUCK_VOLTAGE_MASK GENMASK(7, 2)
97 #define LDO_BUCK_PULL_DOWN_MASK GENMASK(1, 0)
158 #define VINLOW_HYST_MASK GENMASK(1, 0)
160 #define VINLOW_THRESHOLD_MASK GENMASK(2, 0)
163 #define VINLOW_CTRL_REG_MASK GENMASK(7, 0)
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_iossm_mailbox.h48 #define IOSSM_CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16)
58 #define INTF_IP_TYPE_MASK GENMASK(31, 29)
59 #define INTF_INSTANCE_ID_MASK GENMASK(28, 24)
63 #define INTF_ECC_ENABLE_TYPE_MASK GENMASK(1, 0)
71 #define INTF_CAPACITY_GBITS_MASK GENMASK(7, 0)
85 #define ECC_ERR_COUNTER_MASK GENMASK(15, 0)
86 #define ECC_ERR_OVERFLOW_MASK GENMASK(31, 16)
89 #define ECC_ERR_IP_TYPE_MASK GENMASK(24, 22)
90 #define ECC_ERR_INSTANCE_ID_MASK GENMASK(21, 17)
91 #define ECC_ERR_SOURCE_ID_MASK GENMASK(16, 10)
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H A Dagilex5_clock_manager.h152 #define CLKMGR_MEM_ADDR_MASK GENMASK(15, 0)
217 #define CLKMGR_CLKSRC_MASK GENMASK(18, 16)
224 #define CLKMGR_PLLCX_DIV_MSK GENMASK(10, 0)
229 #define CLKMGR_MAINPLL_NOCDIV_L4MP_MASK GENMASK(5, 4)
234 #define CLKMGR_MAINPLL_NOCDIV_L4SP_MASK GENMASK(7, 6)
239 #define CLKMGR_MAINPLL_NOCDIV_SPHY_MASK GENMASK(17, 16)
245 #define CLKMGR_MAINPLL_NOCDIV_L4SYSFREE_MASK GENMASK(3, 2)
255 #define CLKMGR_ALTERA_EMACACTR_CLK_SRC_MASK GENMASK(18, 16)
283 #define CLKMGR_PLLM_MDIV_MASK GENMASK(9, 0)
286 #define CLKMGR_PLLGLOB_AREFCLKDIV_MASK GENMASK(11, 8)
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/rk3399_ARM-atf/plat/intel/soc/common/drivers/ddr/
H A Dddr.h54 #define CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16)
56 #define STATUS_CMD_RESPONSE_ERROR_MASK GENMASK(7, 5)
58 #define STATUS_GENERAL_ERROR_MASK GENMASK(4, 1)
73 #define CMD_TARGET_IP_TYPE_MASK GENMASK(31, 29)
75 #define CMD_TARGET_IP_INSTANCE_ID_MASK GENMASK(28, 24)
77 #define CMD_TYPE_MASK GENMASK(23, 16)
79 #define CMD_OPCODE_MASK GENMASK(15, 0)
/rk3399_ARM-atf/include/drivers/cadence/
H A Dcdns_nand.h163 #define CNF_ECC_CORR_STR_MASK GENMASK(10, 8)
172 #define CNF_SECTOR_OFFSET_MASK GENMASK(31, 16)
179 #define CNF_LAST_SECTOR_MASK GENMASK(31, 16)
219 #define CNF_MFR_ID_MASK GENMASK(7, 0)
220 #define CNF_DEV_ID_MASK GENMASK(23, 16)
273 #define RESYNC_IDLE_CNT_MASK GENMASK(7, 0)
281 #define RESYNC_HIGH_CNT_MASK GENMASK(11, 8)
320 #define CNF_MARKER_MASK GENMASK(31, 16)
/rk3399_ARM-atf/plat/allwinner/sun50i_h616/
H A Dsunxi_h616_dtb.c22 #define CCSIDR_SETS_MASK GENMASK(14, 0)
24 #define CCSIDR_ASSOC_MASK GENMASK(9, 0)
26 #define CCSIDR_LSIZE_MASK GENMASK(2, 0)
/rk3399_ARM-atf/drivers/st/usb/
H A Dstm32mp1_usb.c68 #define OTG_DAINT_OUT_MASK GENMASK(31, 16)
70 #define OTG_DAINT_IN_MASK GENMASK(15, 0)
87 #define OTG_GUSBCFG_TRDT GENMASK(13, 10)
115 #define OTG_GRXSTSP_EPNUM GENMASK(3, 0)
116 #define OTG_GRXSTSP_BCNT GENMASK(14, 4)
118 #define OTG_GRXSTSP_PKTSTS GENMASK(20, 17)
128 #define OTG_GLPMCFG_BESL GENMASK(5, 2)
131 #define OTG_DCFG_DAD GENMASK(10, 4)
141 #define OTG_DSTS_ENUMSPD_MASK GENMASK(2, 1)
161 #define OTG_DIEPCTL_MPSIZ GENMASK(10, 0)
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/rk3399_ARM-atf/plat/amd/versal2/include/
H A Ddef.h48 # define PMC_VERSION GENMASK(7U, 0U)
49 # define PS_VERSION GENMASK(15U, 8U)
50 # define RTL_VERSION GENMASK(23U, 16U)
51 # define PLATFORM_MASK GENMASK(27U, 24U)
52 # define PLATFORM_VERSION_MASK GENMASK(31U, 28U)
/rk3399_ARM-atf/plat/st/stm32mp1/
H A Dstm32mp1_dbgmcu.c22 #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
23 #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
H A Dstm32mp1_syscfg.c52 #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
54 #define SYSCFG_BOOTR_BOOTPD_MASK GENMASK(6, 4)
82 #define SYSCFG_CMPCR_RANSRC GENMASK(19, 16)
84 #define SYSCFG_CMPCR_RAPSRC GENMASK(23, 20)
116 #define SYSCFG_IDC_DEV_ID_MASK GENMASK(11, 0)
117 #define SYSCFG_IDC_REV_ID_MASK GENMASK(31, 16)
/rk3399_ARM-atf/services/std_svc/rmmd/
H A Drmmd_mem.c16 #define MEMRESERVE_FLAGS_MASK GENMASK(MEMRESERVE_NR_FLAGS - 1, 0)
20 #define MEMRESERVE_FLAGS(x) ((x) & GENMASK(MEMRESERVE_ALIGNMENT_SHIFT - 1, 0))
/rk3399_ARM-atf/drivers/st/etzpc/
H A Detzpc.c25 #define ETZPC_MODE_MASK GENMASK(1, 0)
27 #define ETZPC_ID_MASK GENMASK(7, 0)
38 #define ETZPC_DECPROT0_MASK GENMASK(1, 0)
74 #define PERIPH_ATTR_MASK GENMASK(2, 0)
/rk3399_ARM-atf/include/drivers/
H A Dmmc.h68 #define EXT_CSD_PART_CONFIG_ACC_MASK GENMASK(2, 0)
72 #define PART_CFG_BOOT_PART_EN_MASK GENMASK(5, 3)
95 #define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0)
96 #define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3)
126 #define SD_SWITCH_ALL_GROUPS_MASK GENMASK(23, 0)
/rk3399_ARM-atf/drivers/st/reset/
H A Dstm32mp2_reset.c20 return ((reset_id & GENMASK(31, 5)) >> 5) * sizeof(uint32_t); in id2reg_offset()
25 return (uint8_t)(reset_id & GENMASK(4, 0)); in id2reg_bit_pos()
H A Dstm32mp1_reset.c21 return ((reset_id & GENMASK(31, 5)) >> 5) * sizeof(uint32_t); in id2reg_offset()
26 return (uint8_t)(reset_id & GENMASK(4, 0)); in id2reg_bit_pos()
/rk3399_ARM-atf/drivers/allwinner/
H A Dsunxi_msgbox.c26 #define FIFO_STAT_MASK GENMASK(0, 0)
29 #define MSG_STAT_MASK GENMASK(2, 0)

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