| #
884a6506 |
| 31-Jan-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "st-nvmem" into integration
* changes:
feat(stm32mp1): manage monotonic counter
feat(stm32mp1): new way to access platform OTP
feat(stm32mp1-fdts): update NVMEM nodes
Merge changes from topic "st-nvmem" into integration
* changes:
feat(stm32mp1): manage monotonic counter
feat(stm32mp1): new way to access platform OTP
feat(stm32mp1-fdts): update NVMEM nodes
refactor(st-drivers): improve BSEC driver
feat(stm32mp1-fdts): add nvmem_layout node and OTP definitions
feat(stm32mp1): add NVMEM layout compatibility definition
show more ...
|
| #
072d7532 |
| 20-May-2019 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
refactor(st-drivers): improve BSEC driver
Rename driver file to BSEC2.
Split header file in IP and feature parts.
Add functions to access BSEC scratch register.
Several corrections and improvements.
refactor(st-drivers): improve BSEC driver
Rename driver file to BSEC2.
Split header file in IP and feature parts.
Add functions to access BSEC scratch register.
Several corrections and improvements.
Probe the driver earlier, especially to check debug features.
Change-Id: I1981536398d598d67a19d2d7766dacc18de72ec1
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
show more ...
|
| #
9b75d947 |
| 04-Jan-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "st_fixes" into integration
* changes:
fix(stm32mp1): do not reopen debug features
refactor(stm32mp1): improve DGBMCU driver
fix(stm32mp1): set reset pulse duration to
Merge changes from topic "st_fixes" into integration
* changes:
fix(stm32mp1): do not reopen debug features
refactor(stm32mp1): improve DGBMCU driver
fix(stm32mp1): set reset pulse duration to 31ms
show more ...
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| #
21cfa453 |
| 15-Sep-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
fix(stm32mp1): do not reopen debug features
On closed chips, it is not allowed to open debug. The BSEC debug
register can not be rewritten.
On open chips, the debug is already open, no need to rewri
fix(stm32mp1): do not reopen debug features
On closed chips, it is not allowed to open debug. The BSEC debug
register can not be rewritten.
On open chips, the debug is already open, no need to rewrite this
register. This part of code is just removed.
An INFO message is displayed if debug is disabled.
The freeze of the watchdog during debug is also removed.
In case of debug, this must be managed by the software that enables
the debugger.
Change-Id: I19fbd3c487bb1018db30fd599cfa94fe5090899f
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
show more ...
|
| #
a24d5947 |
| 19-Sep-2019 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
refactor(stm32mp1): improve DGBMCU driver
Add function headers to improve readability.
Add asserts when required.
Use RCC_BASE address.
Change-Id: Ia545293f00167b6276331a986ea7aa08c006e004
Signed-o
refactor(stm32mp1): improve DGBMCU driver
Add function headers to improve readability.
Add asserts when required.
Use RCC_BASE address.
Change-Id: Ia545293f00167b6276331a986ea7aa08c006e004
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
show more ...
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| #
0289ab9e |
| 10-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "yg/stm32mp1_wdg_updates" into integration
* changes:
mmc: stm32_sdmmc2: correctly manage block size
mmc: stm32_sdmmc2: manage max-frequency property from DT
stm32mp1:
Merge changes from topic "yg/stm32mp1_wdg_updates" into integration
* changes:
mmc: stm32_sdmmc2: correctly manage block size
mmc: stm32_sdmmc2: manage max-frequency property from DT
stm32mp1: move check_header() to common code
stm32mp1: keep console during runtime
stm32mp1: sp_min: initialize MMU and cache earlier
stm32mp1: add support for LpDDR3
stm32mp1: use a common function to check spinlock is available
clk: stm32mp: enable RTCAPB clock for dual-core chips
stm32mp1: check if the SoC is single core
stm32mp1: print information about board
stm32mp1: print information about SoC
stm32mp1: add watchdog support
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| #
dec286dd |
| 04-Jun-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: print information about SoC
This information is located in DBGMCU registers.
Change-Id: I480aa046fed9992e3d9665b1f0520bc4b6cfdf30
Signed-off-by: Yann Gautier <yann.gautier@st.com>
|
| #
73680c23 |
| 04-Jun-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: add watchdog support
Introduce driver for STM32 IWDG peripheral (Independent Watchdog).
It is configured according to device tree content and should be enabled
from there.
The watchdog is
stm32mp1: add watchdog support
Introduce driver for STM32 IWDG peripheral (Independent Watchdog).
It is configured according to device tree content and should be enabled
from there.
The watchdog is not started by default. It can be started after an HW
reset if the dedicated OTP is fused.
The watchdog also needs to be frozen if a debugger is attached.
This is done by configuring the correct bits in DBGMCU.
This configuration is allowed by checking BSEC properties.
An increase of BL2 size is also required when adding this new code.
Change-Id: Ide7535d717885ce2f9c387cf17afd8b5607f3e7f
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
show more ...
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