| #
7300a4d1 |
| 30-Jul-2024 |
Andre Przywara <andre.przywara@arm.com> |
fix(allwinner): dtb: check for correct error condition
In sunxi_soc_fdt_fixup(), we check for the value of "ret" again, after
calling fdt_node_offset_by_phandle(), even though the error value of
tha
fix(allwinner): dtb: check for correct error condition
In sunxi_soc_fdt_fixup(), we check for the value of "ret" again, after
calling fdt_node_offset_by_phandle(), even though the error value of
that lands in "node".
Check for "node" being non-negative instead, to properly detect any
errors here.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I57c1406388dbe11d343038da173019519e18af3e
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| #
55b4c5ce |
| 29-Jul-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "h616_pmics" into integration
* changes:
feat(allwinner): adjust H616 L2 cache size in DTB
feat(allwinner): h616: add support for AXP717 PMIC
feat(allwinner): h616: ad
Merge changes from topic "h616_pmics" into integration
* changes:
feat(allwinner): adjust H616 L2 cache size in DTB
feat(allwinner): h616: add support for AXP717 PMIC
feat(allwinner): h616: add support for AXP313 PMIC
feat(allwinner): h616: add I2C PMIC support
refactor(allwinner): h616: prepare for more than one PMIC model
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| #
ee5b26fd |
| 01-May-2024 |
Andre Przywara <andre.przywara@arm.com> |
feat(allwinner): adjust H616 L2 cache size in DTB
The Allwinner H616 and its siblings come in different die revisions,
some have 256 KB of L2 cache, some have 1 MB. This prevents a single
static cac
feat(allwinner): adjust H616 L2 cache size in DTB
The Allwinner H616 and its siblings come in different die revisions,
some have 256 KB of L2 cache, some have 1 MB. This prevents a single
static cache description in the devicetree.
Use the cache size ID register (CCSIDR_EL1) to query the topology of the
L2 cache, and adjust the cache-sets and cache-size properties in the L2
cache DT node accordingly.
The ARM ARM does not promise (anymore) that the cache size can be derived
*architecturally* from this register, but the reading is definitely
correct for the Arm Cortex-A53 core used.
Change-Id: Id7dc324d783b8319fe5df6164be2f941d4cac82d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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