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Searched refs:BL1_RW_BASE (Results 1 – 24 of 24) sorted by relevance

/rk3399_ARM-atf/bl1/
H A Dbl1.ld.S23 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE
114 . = BL1_RW_BASE;
116 ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
/rk3399_ARM-atf/plat/hisilicon/poplar/include/
H A Dpoplar_layout.h121 #define BL1_RW_BASE (LLOADER_TEXT_BASE + BL1_RW_OFFSET) macro
122 #define BL1_RW_LIMIT (BL1_RW_BASE + BL1_RW_SIZE)
/rk3399_ARM-atf/plat/rpi/rpi3/include/
H A Dplatform_def.h171 #define BL1_RW_BASE (BL1_RW_LIMIT - PLAT_MAX_BL1_RW_SIZE) macro
178 #define RPI3_MAP_BL1_RW MAP_REGION_FLAT(BL1_RW_BASE, \
179 BL1_RW_LIMIT - BL1_RW_BASE, \
203 #define BL31_PROGBITS_LIMIT BL1_RW_BASE
/rk3399_ARM-atf/include/plat/nuvoton/common/
H A Dnpcm845x_arm_def.h305 BL1_RW_BASE, BL1_RW_LIMIT - BL1_RW_BASE, \
425 #define BL1_RW_BASE (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE - \ macro
434 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE)
450 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
451 #define BL2_LIMIT BL1_RW_BASE
/rk3399_ARM-atf/plat/common/
H A Dplat_bl1_common.c125 assert(BL1_RW_BASE > bl1_mem_layout->total_base); in bl1_plat_calc_bl2_layout()
127 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; in bl1_plat_calc_bl2_layout()
/rk3399_ARM-atf/include/plat/marvell/armada/a3k/common/
H A Dmarvell_def.h148 #define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \ macro
173 #define BL31_PROGBITS_LIMIT BL1_RW_BASE
/rk3399_ARM-atf/plat/hisilicon/hikey960/aarch64/
H A Dhikey960_common.c29 #define MAP_BL1_RW MAP_REGION_FLAT(BL1_RW_BASE, \
30 BL1_RW_LIMIT - BL1_RW_BASE, \
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/include/nrd3/
H A Dnrd_css_fw_def3.h86 BL1_RW_BASE, \
87 BL1_RW_LIMIT - BL1_RW_BASE, \
H A Dnrd_plat_arm_def3.h562 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ macro
573 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
574 #define BL2_LIMIT BL1_RW_BASE
/rk3399_ARM-atf/include/plat/marvell/armada/a8k/common/
H A Dmarvell_def.h179 #define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \ macro
208 #define BL31_PROGBITS_LIMIT BL1_RW_BASE
/rk3399_ARM-atf/plat/arm/board/fvp_ve/include/
H A Dplatform_def.h207 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ macro
221 #define BL2_BASE (BL1_RW_BASE - FVP_VE_MAX_BL2_SIZE)
222 #define BL2_LIMIT BL1_RW_BASE
/rk3399_ARM-atf/plat/arm/board/a5ds/include/
H A Dplatform_def.h224 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ macro
236 #define BL2_BASE (BL1_RW_BASE - A5DS_MAX_BL2_SIZE)
237 #define BL2_LIMIT BL1_RW_BASE
/rk3399_ARM-atf/include/plat/arm/common/
H A Darm_def.h378 BL1_RW_BASE, \
379 BL1_RW_LIMIT - BL1_RW_BASE, \
574 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ macro
584 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE)
611 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
612 #define BL2_LIMIT BL1_RW_BASE
/rk3399_ARM-atf/plat/brcm/board/stingray/include/
H A Dplatform_def.h101 #define BL1_RW_BASE (BRCM_BL_RAM_BASE) macro
102 #define BL1_RW_LIMIT (BL1_RW_BASE + 0x12000)
/rk3399_ARM-atf/plat/qemu/qemu_sbsa/include/
H A Dplatform_def.h131 #define BL1_RW_BASE (BL1_RW_LIMIT - BL1_SIZE) macro
153 #define BL31_LIMIT (BL1_RW_BASE - FW_HANDOFF_SIZE - \
155 #define BL31_PROGBITS_LIMIT BL1_RW_BASE
/rk3399_ARM-atf/plat/hisilicon/hikey/include/
H A Dhikey_layout.h40 #define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_8000 */ macro
/rk3399_ARM-atf/plat/hisilicon/hikey960/include/
H A Dplatform_def.h54 #define BL1_RW_BASE (BL1_RO_LIMIT) /* 1AC2_0000 */ macro
/rk3399_ARM-atf/plat/hisilicon/poplar/
H A Dbl1_plat_setup.c76 bl1_tzram_layout.total_base = BL1_RW_BASE; in bl1_early_platform_setup()
/rk3399_ARM-atf/plat/qemu/qemu/include/
H A Dplatform_def.h135 #define BL1_RW_BASE (BL1_RW_LIMIT - 0x12000) macro
155 #define BL31_PROGBITS_LIMIT BL1_RW_BASE
/rk3399_ARM-atf/plat/hisilicon/hikey/
H A Dhikey_bl1_setup.c55 bl1_tzram_layout.total_base = BL1_RW_BASE; in bl1_early_platform_setup()
/rk3399_ARM-atf/plat/intel/soc/common/include/
H A Dplatform_def.h121 #define BL1_RW_BASE (0xffe10000) macro
/rk3399_ARM-atf/plat/hisilicon/hikey960/
H A Dhikey960_bl1_setup.c87 bl1_tzram_layout.total_base = BL1_RW_BASE; in bl1_early_platform_setup()
/rk3399_ARM-atf/docs/design/
H A Dfirmware-design.rst152 to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``.
/rk3399_ARM-atf/docs/
H A Dporting-guide.rst205 - **#define : BL1_RW_BASE**