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/optee_os/core/arch/arm/kernel/
H A Dentry_a64.S31 cmp x0, #CFG_TEE_CORE_NB_CORE
34 add x0, x0, #1
37 mul x1, x0, x1
42 add x0, x0, x2
45 add sp, x1, x0
48 mov sp, x0
63 mrs x0, sctlr_el1
64 orr x0, x0, #SCTLR_I
65 orr x0, x0, #SCTLR_SA
66 orr x0, x0, #SCTLR_SPAN
[all …]
H A Dvfp_a64.S10 stp q0, q1, [x0, #16 * 0]
11 stp q2, q3, [x0, #16 * 2]
12 stp q4, q5, [x0, #16 * 4]
13 stp q6, q7, [x0, #16 * 6]
14 stp q8, q9, [x0, #16 * 8]
15 stp q10, q11, [x0, #16 * 10]
16 stp q12, q13, [x0, #16 * 12]
17 stp q14, q15, [x0, #16 * 14]
18 stp q16, q17, [x0, #16 * 16]
19 stp q18, q19, [x0, #16 * 18]
[all …]
H A Darch_scall_a64.S16 uint64_t x0;
35 stp x0, x1, [sp, #SC_REC_X0]
39 ldr x2, [x0, #THREAD_SCALL_REG_SPSR]
43 ldp x5, x6, [x0, #THREAD_SCALL_REG_X5]
60 lsl x0, x6, #2
62 cmp x1, x0
63 csel x0, x1, x0, ge
64 add x0, x0, #0xf
65 and x0, x0, #0xfffffffffffffff0
66 sub sp, sp, x0
[all …]
H A Dthread_a64.S69 load_xregs x0, THREAD_CTX_REGS_SP, 1, 3
70 load_xregs x0, THREAD_CTX_REGS_X4, 4, 30
74 ldr x1, [x0, THREAD_CTX_REGS_TPIDR_EL0]
78 load_xregs x0, THREAD_CTX_REGS_APIAKEY_HI, 1, 2
88 load_xregs x0, THREAD_CTX_REGS_X1, 1, 3
89 ldr x0, [x0, THREAD_CTX_REGS_X0]
93 load_xregs x0, THREAD_CTX_REGS_X1, 1, 3
94 ldr x0, [x0, THREAD_CTX_REGS_X0]
115 push x0, xzr
116 mov x8, x0
[all …]
H A Dmisc_a64.S13 mrs x0, mpidr_el1
22 and x0, x0, x1
31 tst x0, #MPIDR_MT_MASK
32 lsl x3, x0, #MPIDR_AFFINITY_BITS
33 csel x3, x3, x0, eq
41 ubfx x0, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
43 add x0, x0, x1, LSL #(CFG_CORE_CLUSTER_SHIFT)
49 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
53 add x0, x0, x1, LSL #(CFG_CORE_THREAD_SHIFT)
H A Dthread_optee_smc_a64.S49 ldr x0, =TEESMC_OPTEED_RETURN_CALL_DONE
59 mov x0, sp
63 ldr x0, =TEESMC_OPTEED_RETURN_CALL_DONE
74 ldr x0, =TEESMC_OPTEED_RETURN_FIQ_DONE
82 mov x1, x0
83 ldr x0, =TEESMC_OPTEED_RETURN_ON_DONE
92 mov x1, x0
93 ldr x0, =TEESMC_OPTEED_RETURN_OFF_DONE
102 mov x1, x0
103 ldr x0, =TEESMC_OPTEED_RETURN_SUSPEND_DONE
[all …]
H A Dtlb_helpers_a64.S21 lsr x0, x0, #TLBI_VA_SHIFT
23 tlbi vaae1is, x0 /* Invalidate tlb by va in inner shareable */
31 lsl x0, x0, #TLBI_ASID_SHIFT
33 tlbi aside1is, x0 /* Invalidate tlb by asid in inner shareable */
34 orr x0, x0, #BIT(TLBI_ASID_SHIFT) /* Select the kernel ASID */
35 tlbi aside1is, x0 /* Invalidate tlb by asid in inner shareable */
H A Dcache_helpers_a64.S30 add x1, x0, x1
32 bic x0, x0, x3
34 dc \op, x0
35 add x0, x0, x2
36 cmp x0, x1
104 add x14, x14, x0, lsl #5 // inner loop is 8x32-bit instructions
105 BTI( add x14, x14, x0, lsl #2) // inner loop is + "bti j" instruction
106 mov x0, x9
110 lsr x1, x0, x2 // extract cache type bits from clidr
228 add x1, x0, x1
[all …]
H A Dthread_spmc_a64.S19 mov_imm x0, FFA_INTERRUPT /* FID */
32 mov_imm x0, FFA_MSG_WAIT /* FID */
73 mov x0, sp
92 mov sp, x0
111 mov x0, sp
124 mov sp, x0
141 push x0, xzr
145 store_xregs x0, THREAD_CTX_REGS_X19, 19, 30
146 mov x19, x0
152 store_xregs x0, THREAD_CTX_REGS_APIAKEY_HI, 1, 2
[all …]
H A Dspin_lock_a64.S67 l2: ldaxr w1, [x0]
69 stxr w1, w2, [x0]
76 mov x1, x0
88 stlr wzr, [x0]
/optee_os/core/arch/arm/dts/
H A Dstm32mp235f-dk-ca35tdcid-resmem.dtsi14 reg = <0x0 0xa000000 0x0 0x20000>;
19 reg = <0x0 0xa020000 0x0 0x20000>;
24 reg = <0x0 0xa040000 0x0 0x1000>;
29 reg = <0x0 0xa041000 0x0 0x1000>;
34 reg = <0x0 0xa042000 0x0 0x1000>;
39 reg = <0x0 0xa043000 0x0 0x1d000>;
44 reg = <0x0 0xa060000 0x0 0x20000>;
49 reg = <0x0 0xa080000 0x0 0x1f000>;
54 reg = <0x0 0xa09f000 0x0 0x1000>;
60 reg = <0x0 0x42000000 0x0 0x1000>;
[all …]
H A Dstm32mp257f-dk-ca35tdcid-resmem.dtsi14 reg = <0x0 0xa000000 0x0 0x20000>;
19 reg = <0x0 0xa020000 0x0 0x20000>;
24 reg = <0x0 0xa040000 0x0 0x1000>;
29 reg = <0x0 0xa041000 0x0 0x1000>;
34 reg = <0x0 0xa042000 0x0 0x1000>;
39 reg = <0x0 0xa043000 0x0 0x1d000>;
44 reg = <0x0 0xa060000 0x0 0x20000>;
49 reg = <0x0 0xa080000 0x0 0x1f000>;
54 reg = <0x0 0xa09f000 0x0 0x1000>;
60 reg = <0x0 0x10000000 0x0 0x10000000>;
[all …]
H A Dstm32mp257f-ev1-ca35tdcid-resmem.dtsi14 reg = <0x0 0xa000000 0x0 0x20000>;
19 reg = <0x0 0xa020000 0x0 0x20000>;
24 reg = <0x0 0xa040000 0x0 0x1000>;
29 reg = <0x0 0xa041000 0x0 0x1f000>;
34 reg = <0x0 0xa060000 0x0 0x20000>;
39 reg = <0x0 0xa080000 0x0 0x1f000>;
44 reg = <0x0 0xa09f000 0x0 0x1000>;
50 reg = <0x0 0x10000000 0x0 0x10000000>;
56 reg = <0x0 0x42000000 0x0 0x1000>;
61 reg = <0x0 0x42001000 0x0 0x1000>;
[all …]
H A Dfsl-lx2160a.dtsi31 reg = <0x0>;
366 arm,psci-suspend-param = <0x0>;
375 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
376 <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
378 <0x0 0x0c0c0000 0 0x2000>, // GICC
379 <0x0 0x0c0d0000 0 0x1000>, // GICH
380 <0x0 0x0c0e0000 0 0x20000>; // GICV
391 reg = <0x0 0x6020000 0 0x20000>;
427 reg = <0x0 0x1080000 0x0 0x1000>;
434 reg = <0x0 0x1090000 0x0 0x1000>;
[all …]
H A Dstm32mp211.dtsi40 reg = <0x0 0x4ac10000 0x0 0x1000>,
41 <0x0 0x4ac20000 0x0 0x2000>,
42 <0x0 0x4ac40000 0x0 0x2000>,
43 <0x0 0x4ac60000 0x0 0x2000>;
96 ranges = <0x0 0x0 0x0 0x80000000>;
/optee_os/core/arch/arm/plat-vexpress/
H A Djuno_core_pos_a64.S12 and x1, x0, #MPIDR_CPU_MASK
13 and x0, x0, #MPIDR_CLUSTER_MASK
14 eor x0, x0, #(1 << MPIDR_CLUSTER_SHIFT)
15 add x0, x1, x0, LSR #6
/optee_os/lib/libutils/isoc/arch/arm/
H A Dsetjmp_a64.S53 #define REG_PAIR(REG1, REG2, OFFS) stp REG1, REG2, [x0, OFFS]
54 #define REG_ONE(REG1, OFFS) str REG1, [x0, OFFS]
60 add x0, x0, #104
75 #define REG_PAIR(REG1, REG2, OFFS) ldp REG1, REG2, [x0, OFFS]
76 #define REG_ONE(REG1, OFFS) ldr REG1, [x0, OFFS]
78 stp x0, x1, [sp, #-16]!
81 add x0, x0, #104
84 ldp x0, x1, [sp], #16
88 stp x0, x1, [sp, #-16]!
89 ldr x0, [x0, 96]
[all …]
/optee_os/core/arch/arm/plat-rcar/
H A Dcore_pos_a64.S22 tst x0, #MPIDR_MT_MASK
23 lsl x3, x0, #MPIDR_AFFINITY_BITS
24 csel x3, x3, x0, eq
31 ubfx x0, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
70 add x0, x0, x1
H A Dromapi_call.S24 mov x19, x0
30 mov x0, sp
44 mov x23, x0
47 mov x0, #DCACHE_OP_CLEAN
74 mov x0, x20 /* x20: uint64_t arg1 */
/optee_os/core/arch/riscv/kernel/
H A Dsemihosting_rv.S17 slli x0, x0, 0x1f
19 srai x0, x0, 0x7
/optee_os/lib/libutils/ext/arch/arm/
H A Dmcount_a64.S46 adjust_pc x0, x0
51 get_pc x0
63 stp x0, x1, [sp]
70 mov x30, x0
73 ldp x0, x1, [sp]
H A Datomic_a64.S11 ldaxr w1, [x0]
13 stxr w2, w1, [x0]
22 ldaxr w1, [x0]
24 stxr w2, w1, [x0]
/optee_os/core/arch/arm/plat-automotive_rd/
H A Drd1ae_core_pos.S11 mov x4, x0
19 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
30 madd x0, x1, x4, x0
/optee_os/core/arch/arm/plat-d06/
H A Dcore_pos_a64.S22 lsr x1, x0, 8
25 lsr x1, x0, 16
28 lsr x1, x0, 20
45 mov x0, x5
/optee_os/core/arch/arm/plat-marvell/otx2/
H A Dcore_pos.S10 ubfx x1, x0, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
13 ubfx x2, x0, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
14 add x0, x1, x2

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