core: change get_core_pos_mpidr() to support hypervisor

The secure hypervisor, such as Hafnium, is expected to manipulate
MPIDR_EL1 to indicate a VCPU ID.

This commit makes get_core_pos_mpidr() not

core: change get_core_pos_mpidr() to support hypervisor

The secure hypervisor, such as Hafnium, is expected to manipulate
MPIDR_EL1 to indicate a VCPU ID.

This commit makes get_core_pos_mpidr() not calculate a CPU ID
using the affinity bitfields of MPIDR_EL1 when there is a hypervisor
in SEL2.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Sungbae Yoo <sungbaey@nvidia.com>

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Generate ELF Note for BTI in all arm64 asm files

Add program property note section in the assembly files to
ensure that when linking them, program property note section
is generated in the final ELF

Generate ELF Note for BTI in all arm64 asm files

Add program property note section in the assembly files to
ensure that when linking them, program property note section
is generated in the final ELF.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: asm: use WEAK_FUNC rather than FUNC + .weak

Some functions are defined in assembler with the FUNC macro (which
contains a .global directive) followed by a .weak directive to make
them weak sym

core: asm: use WEAK_FUNC rather than FUNC + .weak

Some functions are defined in assembler with the FUNC macro (which
contains a .global directive) followed by a .weak directive to make
them weak symbols. While this works fine with GCC and Clang up to
11.0.0, Clang 12.0.0 emits a warning:

AS out/arm/core/arch/arm/kernel/misc_a32.o
core/arch/arm/kernel/misc_a32.S:58:1: warning: get_core_pos_mpidr changed binding to STB_WEAK
.weak get_core_pos_mpidr
^

Fix this by using the newly introduced WEAK_FUNC macro.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add support for CFG_CORE_ASLR

Adds support for CFG_CORE_ASLR to load TEE Core at a random address.
ASLR makes the exploitation of memory corruption vulnerabilities more
difficult.

Paging is c

core: add support for CFG_CORE_ASLR

Adds support for CFG_CORE_ASLR to load TEE Core at a random address.
ASLR makes the exploitation of memory corruption vulnerabilities more
difficult.

Paging is currently not supported with CFG_CORE_ASLR=y.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: Add support for multi-threaded MPIDR values

If the MT bit is set the affinities are shifted in the MPIDR register
so the get_core_pos_mpidr function needs to be modified accordingly.
This is n

core: Add support for multi-threaded MPIDR values

If the MT bit is set the affinities are shifted in the MPIDR register
so the get_core_pos_mpidr function needs to be modified accordingly.
This is necessary to make OP-TEE to be able to run on multi-threaded
systems. The number of threads/core can be modified by the
CFG_CORE_THREAD_SHIFT makefile parameter. The default value is the
existing single threaded mode.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Move .weak directive after the symbol definition

Clang ignores the .weak directive if it appears before the symbol is
defined. Fix the few places where it happens.

Signed-off-by: Jerome Forissier <

Move .weak directive after the symbol definition

Clang ignores the .weak directive if it appears before the symbol is
defined. Fix the few places where it happens.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: assert foreign interrupts are masked in get_core_pos()

This change modifies get_core_pos() so that calling the routine
from C source asserts the foreign interrupts are masked when
the function

core: assert foreign interrupts are masked in get_core_pos()

This change modifies get_core_pos() so that calling the routine
from C source asserts the foreign interrupts are masked when
the function is called, preventing a cpu migration while reading
current core position.

There is no assertion of foreign interrupt masking for such calls to
get_core_pos() from assembly sources.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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Remove 'All rights reserved' from Linaro files

The text 'All rights reserved' is useless [1]. The Free Software
Foundation's REUSE Initiative best practices document [2] does not
contain these words

Remove 'All rights reserved' from Linaro files

The text 'All rights reserved' is useless [1]. The Free Software
Foundation's REUSE Initiative best practices document [2] does not
contain these words. Therefore, we can safely remove the text from the
files that are owned by Linaro.

Generated by:
spdxify.py --linaro-only --strip-arr optee_os/

Link: [1] https://en.wikipedia.org/wiki/All_rights_reserved
Link: [2] https://reuse.software/practices/
Link: [3] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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Remove license notice from Linaro files

Now that we have added SPDX identifiers, we can safely remove the
verbose license text from the files that are owned by Linaro.

Generated by [1]:
spdxify.p

Remove license notice from Linaro files

Now that we have added SPDX identifiers, we can safely remove the
verbose license text from the files that are owned by Linaro.

Generated by [1]:
spdxify.py --linaro-only --strip-license-text optee_os/

Link: [1] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] wa

Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] was used to double check the license matching
code in the Python script. All the licenses detected by scancode are
either detected by spdxify.py, or have no SPDX identifier, or are false
matches.

Link: [1] https://spdx.org/licenses/
Link: [2] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Link: [3] https://github.com/nexB/scancode-toolkit
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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core: Make core_pos more generic

The function core_pos() assumes 4 cores per cluster, this may not
be true for all platforms. Define CFG_CORE_CLUSTER_SHIFT to be
=log2(cores/cluster) and allow setti

core: Make core_pos more generic

The function core_pos() assumes 4 cores per cluster, this may not
be true for all platforms. Define CFG_CORE_CLUSTER_SHIFT to be
=log2(cores/cluster) and allow setting this from platform config.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: introduce get_core_pos_mpidr()

Adds
size_t get_core_pos_mpidr(uint32_t mpidr);
which translates from mpdir to core position, like get_core_pos() does
for the calling core.

get_core_pos_mpidr(

core: introduce get_core_pos_mpidr()

Adds
size_t get_core_pos_mpidr(uint32_t mpidr);
which translates from mpdir to core position, like get_core_pos() does
for the calling core.

get_core_pos_mpidr() a weak function to
allow platforms to override the implementation.

get_core_pos() now uses get_core_pos_mpidr() internally to calculate the
core position without using any stack.

With get_core_pos_mpidr() all the platform specific implementations of
get_core_pos() has been replaced with get_core_pos_mpidr() and
get_core_pos() is not weak any longer to avoid unexpected runtime errors
in out of tree rebased platforms.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU v8)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm: add Aarch64 (aka ARM64) support

* Adds support for ARM64 in plat-vexpress
* The name of the ARM64 instruction set is, hence _a64.S suffix to ARM64
assembly files to keep them apart from the A

arm: add Aarch64 (aka ARM64) support

* Adds support for ARM64 in plat-vexpress
* The name of the ARM64 instruction set is, hence _a64.S suffix to ARM64
assembly files to keep them apart from the A32 assembly files.
* ARM64 specific C code is inside #ifdef ARM64

The ARM64 port has all features of the ARM32 port with the exception of:
* Paging not supported
* No crypto ARMv8 crypto extensions implemented

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP, Juno)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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