core: riscv: Add semihosting.S for semihosting instructions

RISC-V architecture has defined the semihosting binary interface, which
consists of a special trap instruction sequence, in:
https://githu

core: riscv: Add semihosting.S for semihosting instructions

RISC-V architecture has defined the semihosting binary interface, which
consists of a special trap instruction sequence, in:
https://github.com/riscv-non-isa/riscv-semihosting

Add semihosting.S into RISC-V kernel folder to implement the trap
instruction sequence.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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