xref: /optee_os/core/arch/riscv/kernel/semihosting_rv.S (revision 6d716a4b4588d0f73662e3b2527b92a12a877bc5)
1*6d716a4bSAlvin Chang/* SPDX-License-Identifier: BSD-2-Clause */
2*6d716a4bSAlvin Chang/*
3*6d716a4bSAlvin Chang * Copyright (c) 2024 Andes Technology Corporation
4*6d716a4bSAlvin Chang */
5*6d716a4bSAlvin Chang
6*6d716a4bSAlvin Chang#include <asm.S>
7*6d716a4bSAlvin Chang
8*6d716a4bSAlvin Chang/*
9*6d716a4bSAlvin Chang * uintptr_t __do_semihosting(uintptr_t op, uintptr_t arg)
10*6d716a4bSAlvin Chang *
11*6d716a4bSAlvin Chang * Refer to RISC-V Semihosting Binary Interface:
12*6d716a4bSAlvin Chang * https://github.com/riscv-non-isa/riscv-semihosting/blob/main/binary-interface.adoc
13*6d716a4bSAlvin Chang */
14*6d716a4bSAlvin ChangFUNC __do_semihosting , : , .identity_map
15*6d716a4bSAlvin Chang.option push
16*6d716a4bSAlvin Chang.option norvc
17*6d716a4bSAlvin Chang	slli	x0, x0, 0x1f
18*6d716a4bSAlvin Chang	ebreak
19*6d716a4bSAlvin Chang	srai    x0, x0, 0x7
20*6d716a4bSAlvin Chang.option pop
21*6d716a4bSAlvin Chang	ret
22*6d716a4bSAlvin ChangEND_FUNC __do_semihosting
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