core: mm: Rename "mva" to "va" for TLB operations

The terminology "mva" is specific for older ARM architecture which has
FCSE extension. To support multiple architecture, it would be good to
rename

core: mm: Rename "mva" to "va" for TLB operations

The terminology "mva" is specific for older ARM architecture which has
FCSE extension. To support multiple architecture, it would be good to
rename "mva" to common terminology, such as "va". This PR renames "mva"
to "va" in TLB operations for ARM64 and RISC-V. For ARM32, "mva" is
reserved because it is really defined in ARM32's documentations.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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Generate ELF Note for BTI in all arm64 asm files

Add program property note section in the assembly files to
ensure that when linking them, program property note section
is generated in the final ELF

Generate ELF Note for BTI in all arm64 asm files

Add program property note section in the assembly files to
ensure that when linking them, program property note section
is generated in the final ELF.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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Add BTI launch pads in aarch64 assembly files

Compiler adds BTI launchpads only in C source files. For
assembly files, BTI launchpad is also required at locations
where "br" is used and at the start

Add BTI launch pads in aarch64 assembly files

Compiler adds BTI launchpads only in C source files. For
assembly files, BTI launchpad is also required at locations
where "br" is used and at the start of the functions. This
needs to be added manually.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add dcache_clean_range_pou()

Adds dcache_clean_range_pou() which cleans the data cache to the point
of unification. This is exactly what's needed when later invalidating
the icache due to upda

core: add dcache_clean_range_pou()

Adds dcache_clean_range_pou() which cleans the data cache to the point
of unification. This is exactly what's needed when later invalidating
the icache due to updates in a page.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: cache_helpers_a{32,64}.S: remove section assignments

Since the FUNC and LOCAL_FUNC assembly macros now assign a section to
each assembly function the explicitly assigned sections in
cache_help

core: cache_helpers_a{32,64}.S: remove section assignments

Since the FUNC and LOCAL_FUNC assembly macros now assign a section to
each assembly function the explicitly assigned sections in
cache_helpers_a{32,64}.S are ignored. So remove the ignored section
assignments.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm.h: add CTR_WORD_SIZE

Adds a common define for the word size used by the CTR (cache type)
register.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jen

arm.h: add CTR_WORD_SIZE

Adds a common define for the word size used by the CTR (cache type)
register.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: update cache helpers

Updates AArch64 and ARMv7 cache helpers from lib/aarch32/cache_helpers.S
and lib/aarch64/cache_helpers.S in ARM-TF,
https://github.com/ARM-software/arm-trusted-firmware/tr

core: update cache helpers

Updates AArch64 and ARMv7 cache helpers from lib/aarch32/cache_helpers.S
and lib/aarch64/cache_helpers.S in ARM-TF,
https://github.com/ARM-software/arm-trusted-firmware/tree/2bd26faf62411c75111fea4b23c542865383b068

The imported routines only covers the inner cache. Already present ARMv7
cache routines are replaced by the new equivalent routines. The AArch64
routines are updated with the resent changes in ARM-TF.

The imported files are modified to better fit into OP-TEE, some
functions and defines are renamed.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey AArch{32,64} pager)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno AArch{32,64} pager)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm: add Aarch64 (aka ARM64) support

* Adds support for ARM64 in plat-vexpress
* The name of the ARM64 instruction set is, hence _a64.S suffix to ARM64
assembly files to keep them apart from the A

arm: add Aarch64 (aka ARM64) support

* Adds support for ARM64 in plat-vexpress
* The name of the ARM64 instruction set is, hence _a64.S suffix to ARM64
assembly files to keep them apart from the A32 assembly files.
* ARM64 specific C code is inside #ifdef ARM64

The ARM64 port has all features of the ARM32 port with the exception of:
* Paging not supported
* No crypto ARMv8 crypto extensions implemented

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP, Juno)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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