11bb92983SJerome Forissier/* SPDX-License-Identifier: BSD-2-Clause */ 2e0cbf7deSJens Wiklander/* 3e0cbf7deSJens Wiklander * Copyright (c) 2015, Linaro Limited 48be2de1aSImre Kis * Copyright (c) 2019, Arm Limited. All rights reserved. 5e0cbf7deSJens Wiklander */ 6e0cbf7deSJens Wiklander 7e0cbf7deSJens Wiklander#include <asm.S> 8e0cbf7deSJens Wiklander#include <arm.h> 900da26ecSAndrew F. Davis#include <platform_config.h> 10e0cbf7deSJens Wiklander 11af8e0424SEtienne Carriere/* size_t __get_core_pos(void); */ 12170e9084SJens WiklanderFUNC __get_core_pos , : , .identity_map 13e0cbf7deSJens Wiklander mrs x0, mpidr_el1 1430372800SJens Wiklander b get_core_pos_mpidr 15af8e0424SEtienne CarriereEND_FUNC __get_core_pos 1630372800SJens Wiklander 1730372800SJens Wiklander/* size_t get_core_pos_mpidr(uint32_t mpidr); */ 185aaab9c0SJerome Forissier/* Let platforms override this if needed */ 195aaab9c0SJerome ForissierWEAK_FUNC get_core_pos_mpidr , : 20*f0489baaSSungbae Yoo#if CFG_CORE_SEL2_SPMC 21*f0489baaSSungbae Yoo mov x1, #MPIDR_VCPU_MASK 22*f0489baaSSungbae Yoo and x0, x0, x1 23*f0489baaSSungbae Yoo#else /* CFG_CORE_SEL2_SPMC */ 248be2de1aSImre Kis /* 258be2de1aSImre Kis * Shift MPIDR value if it's not already shifted. 268be2de1aSImre Kis * Using logical shift ensures AFF0 to be filled with zeroes. 278be2de1aSImre Kis * This part is necessary even if CFG_CORE_THREAD_SHIFT is 0 because 288be2de1aSImre Kis * MT bit can be set on single threaded systems where all the AFF0 298be2de1aSImre Kis * values are zeroes. 308be2de1aSImre Kis */ 318be2de1aSImre Kis tst x0, #MPIDR_MT_MASK 328be2de1aSImre Kis lsl x3, x0, #MPIDR_AFFINITY_BITS 338be2de1aSImre Kis csel x3, x3, x0, eq 348be2de1aSImre Kis 358be2de1aSImre Kis /* 368be2de1aSImre Kis * At this point the MPIDR layout is always shifted so it looks 378be2de1aSImre Kis * as follows AFF2 -> cluster, AFF1 -> core, AFF0 -> thread 388be2de1aSImre Kis */ 398be2de1aSImre Kis#if CFG_CORE_THREAD_SHIFT == 0 4000da26ecSAndrew F. Davis /* Calculate CorePos = (ClusterId * (cores/cluster)) + CoreId */ 418be2de1aSImre Kis ubfx x0, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS 428be2de1aSImre Kis ubfx x1, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS 438be2de1aSImre Kis add x0, x0, x1, LSL #(CFG_CORE_CLUSTER_SHIFT) 448be2de1aSImre Kis#else 458be2de1aSImre Kis /* 468be2de1aSImre Kis * Calculate CorePos = 478be2de1aSImre Kis * ((ClusterId * (cores/cluster)) + CoreId) * (threads/core) + ThreadId 488be2de1aSImre Kis */ 498be2de1aSImre Kis ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS 508be2de1aSImre Kis ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS 518be2de1aSImre Kis ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS 528be2de1aSImre Kis add x1, x1, x2, LSL #(CFG_CORE_CLUSTER_SHIFT) 538be2de1aSImre Kis add x0, x0, x1, LSL #(CFG_CORE_THREAD_SHIFT) 548be2de1aSImre Kis#endif 55*f0489baaSSungbae Yoo#endif 568be2de1aSImre Kis 57e0cbf7deSJens Wiklander ret 5830372800SJens WiklanderEND_FUNC get_core_pos_mpidr 59181f8492SRuchika Gupta 60181f8492SRuchika GuptaBTI(emit_aarch64_feature_1_and GNU_PROPERTY_AARCH64_FEATURE_1_BTI) 61