Home
last modified time | relevance | path

Searched refs:io_clrsetbits32 (Results 1 – 25 of 42) sorted by relevance

12

/optee_os/core/drivers/clk/sam/
H A Dclk-sam9x60-pll.c103 io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT, in sam9x60_frac_pll_set()
138 io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT, in sam9x60_frac_pll_set()
145 io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT, in sam9x60_frac_pll_set()
168 io_clrsetbits32(frac->core.base + AT91_PMC_PLL_UPDT, in sam9x60_frac_pll_unprepare()
179 io_clrsetbits32(frac->core.base + AT91_PMC_PLL_UPDT, in sam9x60_frac_pll_unprepare()
238 io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT, in sam9x60_frac_pll_set_rate_chg()
245 io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT, in sam9x60_frac_pll_set_rate_chg()
254 io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT, in sam9x60_frac_pll_set_rate_chg()
283 io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT, in sam9x60_div_pll_set_div()
286 io_clrsetbits32(regmap + AT91_PMC_PLL_CTRL0, in sam9x60_div_pll_set_div()
[all …]
H A Dat91_utmi.c73 io_clrsetbits32(utmi->sfr_base + AT91_SFR_UTMICKTRIM, in clk_utmi_enable()
80 io_clrsetbits32(utmi->pmc_base + AT91_CKGR_UCKR, uckr, uckr); in clk_utmi_enable()
176 io_clrsetbits32(utmi->pmc_base + AT91_PMC_XTALF, AT91_PMC_XTALF_XTALF, in clk_utmi_sama7g5_prepare()
H A Dat91_audio_pll.c83 io_clrsetbits32(frac->base + AT91_PMC_AUDIO_PLL1, in clk_audio_pll_frac_enable()
90 io_clrsetbits32(frac->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_enable()
103 io_clrsetbits32(apad_ck->base + AT91_PMC_AUDIO_PLL1, in clk_audio_pll_pad_enable()
106 io_clrsetbits32(apad_ck->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_pad_enable()
116 io_clrsetbits32(apmc_ck->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_pmc_enable()
H A Dat91_main.c51 io_clrsetbits32(osc->base + AT91_CKGR_MOR, in pmc_main_rc_osc_enable()
70 io_clrsetbits32(osc->base + AT91_CKGR_MOR, in pmc_main_rc_osc_disable()
181 io_clrsetbits32(pmc->base + AT91_CKGR_MOR, in pmc_register_main_osc()
262 io_clrsetbits32(pmc->base + AT91_CKGR_MOR, in clk_sam9x5_main_set_parent()
H A Dat91_usb.c45 io_clrsetbits32(usb->base + AT91_PMC_USB, usb->usbs_mask, index); in at91sam9x5_clk_usb_set_parent()
72 io_clrsetbits32(usb->base + AT91_PMC_USB, AT91_PMC_OHCIUSBDIV, in at91sam9x5_clk_usb_set_rate()
H A Dat91_programmable.c65 io_clrsetbits32(prog->base + AT91_PMC_PCKR(prog->id), mask, pckr); in clk_programmable_set_parent()
119 io_clrsetbits32(prog->base + AT91_PMC_PCKR(prog->id), in clk_programmable_set_rate()
H A Dat91_pll.c81 io_clrsetbits32(pll->base + AT91_PMC_PLLICPR, PLL_ICPR_MASK(id), in clk_pll_enable()
85 io_clrsetbits32(pll->base + offset, layout->pllr_mask, in clk_pll_enable()
101 io_clrsetbits32(pll->base + PLL_REG(pll->id), mask, ~mask); in clk_pll_disable()
H A Dat91_plldiv.c35 io_clrsetbits32(pmc->base + AT91_PMC_MCKR, AT91_PMC_PLLADIV2, in clk_plldiv_set_rate()
H A Dat91_peripheral.c65 io_clrsetbits32(periph->base + periph->layout->offset, in clk_sam9x5_peripheral_enable()
84 io_clrsetbits32(periph->base + periph->layout->offset, in clk_sam9x5_peripheral_disable()
H A Dat91_h32mx.c45 io_clrsetbits32(pmc->base + AT91_PMC_MCKR, AT91_PMC_H32MXDIV, mckr); in clk_sama5d4_h32mx_set_rate()
H A Dat91_generated.c37 io_clrsetbits32(gck->base + gck->layout->offset, in clk_generated_enable()
55 io_clrsetbits32(gck->base + gck->layout->offset, AT91_PMC_PCR_GCKEN, in clk_generated_disable()
H A Dat91_i2s_mux.c33 io_clrsetbits32(mux->sfr_base + AT91_SFR_I2SCLKSEL, in clk_i2s_mux_set_parent()
/optee_os/core/drivers/
H A Dstm32_ipcc.c145 io_clrsetbits32(ipcc_d->base + IPCC_C1PRIVCFGR, in apply_rif_config()
147 io_clrsetbits32(ipcc_d->base + IPCC_C1SECCFGR, in apply_rif_config()
151 io_clrsetbits32(ipcc_d->base + IPCC_C2PRIVCFGR, in apply_rif_config()
153 io_clrsetbits32(ipcc_d->base + IPCC_C2SECCFGR, in apply_rif_config()
183 io_clrsetbits32(ipcc_d->base + IPCC_C1CIDCFGR, in apply_rif_config()
210 io_clrsetbits32(ipcc_d->base + IPCC_C2CIDCFGR, in apply_rif_config()
H A Dbcm_hwrng.c35 io_clrsetbits32(bcm_hwrng_base + RNG_CTRL_OFFSET, in bcm_hwrng_reset()
43 io_clrsetbits32(bcm_hwrng_base + RNG_CTRL_OFFSET, in bcm_hwrng_reset()
H A Dstm32_hsem.c95 io_clrsetbits32(hsem_d->base + HSEM_SECCFGR, in apply_rif_config()
98 io_clrsetbits32(hsem_d->base + HSEM_PRIVCFGR, in apply_rif_config()
114 io_clrsetbits32(hsem_d->base + HSEM_CnCIDCFGR(i + 1), in apply_rif_config()
163 io_clrsetbits32(hsem_d->base + HSEM_GpCIDCFGR(i), in apply_rif_config()
H A Dstm32_shared_io.c36 io_clrsetbits32(va, clr, set); in io_clrsetbits32_stm32shregs()
H A Dstm32_fmc.c170 io_clrsetbits32(fmc_d->base + _FMC_PRIVCFGR, _FMC_PRIVCFGR_MASK, in apply_rif_config()
172 io_clrsetbits32(fmc_d->base + _FMC_SECCFGR, _FMC_SECCFGR_MASK, in apply_rif_config()
182 io_clrsetbits32(fmc_d->base + _FMC_CIDCFGR(i), in apply_rif_config()
398 io_clrsetbits32(fmc_d->base + _FMC_CFGR, in configure_fmc()
H A Dstm32_hpdma.c162 io_clrsetbits32(hpdma_d->base + _HPDMA_PRIVCFGR, _HPDMA_PRIVCFGR_MASK & in apply_rif_config()
165 io_clrsetbits32(hpdma_d->base + _HPDMA_SECCFGR, _HPDMA_SECCFGR_MASK & in apply_rif_config()
196 io_clrsetbits32(hpdma_d->base + _HPDMA_CIDCFGR(i), in apply_rif_config()
H A Dstm32_gpio.c338 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, in stm32_gpio_set_direction()
381 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, in stm32_gpio_configure()
385 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, in stm32_gpio_configure()
626 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, in set_gpio_cfg()
631 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), in set_gpio_cfg()
635 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, in set_gpio_cfg()
640 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), in set_gpio_cfg()
645 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, in set_gpio_cfg()
651 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, in set_gpio_cfg()
657 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); in set_gpio_cfg()
[all …]
H A Dmvebu_uart.c132 io_clrsetbits32(base + UART_BAUD_REG, 0x3FF, dll); in mvebu_uart_init()
H A Dstm32_tamp.c754 io_clrsetbits32(base + _TAMP_PRIVCFGR, access_mask_priv_reg, privcfgr); in apply_rif_config()
755 io_clrsetbits32(base + _TAMP_SECCFGR, access_mask_sec_reg, seccfgr); in apply_rif_config()
764 io_clrsetbits32(base + _TAMP_CIDCFGR(i), in apply_rif_config()
787 io_clrsetbits32(base + _TAMP_BKPRIFR(1), _TAMP_BKPRIFR_1_MASK, in stm32_tamp_apply_bkpr_rif_conf()
789 io_clrsetbits32(base + _TAMP_BKPRIFR(2), _TAMP_BKPRIFR_2_MASK, in stm32_tamp_apply_bkpr_rif_conf()
791 io_clrsetbits32(base + _TAMP_BKPRIFR(3), _TAMP_BKPRIFR_3_MASK, in stm32_tamp_apply_bkpr_rif_conf()
844 io_clrsetbits32(base + _TAMP_SECCFGR, in stm32_tamp_set_secure_bkpregs()
849 io_clrsetbits32(base + _TAMP_SECCFGR, in stm32_tamp_set_secure_bkpregs()
854 io_clrsetbits32(base + _TAMP_SMCR, in stm32_tamp_set_secure_bkpregs()
859 io_clrsetbits32(base + _TAMP_SMCR, in stm32_tamp_set_secure_bkpregs()
[all …]
/optee_os/core/drivers/firewall/
H A Dstm32_risab.c195 io_clrsetbits32(base + _RISAB_PGy_SECCFGR(i), in set_block_seccfgr()
208 io_clrsetbits32(base + _RISAB_PGy_PRIVCFGR(i), in set_block_dprivcfgr()
227 io_clrsetbits32(base + _RISAB_PGy_CIDCFGR(i), in set_cidcfgr()
250 io_clrsetbits32(base + _RISAB_CIDxRDCFGR(i), mask, in set_read_conf()
272 io_clrsetbits32(base + _RISAB_CIDxWRCFGR(i), mask, in set_write_conf()
288 io_clrsetbits32(base + _RISAB_CIDxPRIVCFGR(i), mask, in set_cid_priv_conf()
/optee_os/core/arch/arm/plat-stm32mp2/drivers/
H A Dstm32mp25_syscfg.c116 io_clrsetbits32(amcr_addr, SYSCFG_OCTOSPIAMCR_OAM_MASK, amcr); in stm32mp25_syscfg_set_amcr()
/optee_os/core/drivers/crypto/stm32/
H A Dstm32_cryp.c424 io_clrsetbits32(ctx->base + _CRYP_CR, _CRYP_CR_ALGOMODE_MSK, in cryp_prepare_key()
437 io_clrsetbits32(ctx->base + _CRYP_CR, _CRYP_CR_ALGOMODE_MSK, in cryp_prepare_key()
586 io_clrsetbits32(ctx->base + _CRYP_CR, _CRYP_CR_GCM_CCMPH_MSK, in do_from_init_to_phase()
618 io_clrsetbits32(ctx->base + _CRYP_CR, _CRYP_CR_GCM_CCMPH_MSK, in do_from_header_to_phase()
1038 io_clrsetbits32(ctx->base + _CRYP_CR, in stm32_cryp_final()
1059 io_clrsetbits32(ctx->base + _CRYP_CR, _CRYP_CR_GCM_CCMPH_MSK, in stm32_cryp_final()
/optee_os/core/drivers/clk/
H A Dclk-stm32mp21.c841 io_clrsetbits32(address, mask, in clk_oscillator_set_drive()
1339 io_clrsetbits32(xbar0cfgr + (0x4 * i), in stm32mp2_clk_xbar_on_hsi()
1447 io_clrsetbits32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK, in clk_stm32_pll_config_output()
1455 io_clrsetbits32(pllxcfgr2, RCC_PLLxCFGR2_FBDIV_MASK, in clk_stm32_pll_config_output()
1458 io_clrsetbits32(pllxcfgr2, RCC_PLLxCFGR2_FREFDIV_MASK, in clk_stm32_pll_config_output()
1460 io_clrsetbits32(pllxcfgr6, RCC_PLLxCFGR6_POSTDIV1_MASK, in clk_stm32_pll_config_output()
1462 io_clrsetbits32(pllxcfgr7, RCC_PLLxCFGR7_POSTDIV2_MASK, in clk_stm32_pll_config_output()
1484 io_clrsetbits32(pllxcfgr5, RCC_PLLxCFGR5_DIVVAL_MASK, in clk_stm32_pll_config_csg()
1486 io_clrsetbits32(pllxcfgr5, RCC_PLLxCFGR5_SPREAD_MASK, in clk_stm32_pll_config_csg()
1736 io_clrsetbits32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel), in flexclkgen_config_channel()
[all …]

12