841 		io_clrsetbits32(address, mask,  in clk_oscillator_set_drive()
1339 		io_clrsetbits32(xbar0cfgr + (0x4 * i),  in stm32mp2_clk_xbar_on_hsi()
1447 		io_clrsetbits32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK,  in clk_stm32_pll_config_output()
1455 	io_clrsetbits32(pllxcfgr2, RCC_PLLxCFGR2_FBDIV_MASK,  in clk_stm32_pll_config_output()
1458 	io_clrsetbits32(pllxcfgr2, RCC_PLLxCFGR2_FREFDIV_MASK,  in clk_stm32_pll_config_output()
1460 	io_clrsetbits32(pllxcfgr6, RCC_PLLxCFGR6_POSTDIV1_MASK,  in clk_stm32_pll_config_output()
1462 	io_clrsetbits32(pllxcfgr7, RCC_PLLxCFGR7_POSTDIV2_MASK,  in clk_stm32_pll_config_output()
1484 	io_clrsetbits32(pllxcfgr5, RCC_PLLxCFGR5_DIVVAL_MASK,  in clk_stm32_pll_config_csg()
1486 	io_clrsetbits32(pllxcfgr5, RCC_PLLxCFGR5_SPREAD_MASK,  in clk_stm32_pll_config_csg()
1736 	io_clrsetbits32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel),  in flexclkgen_config_channel()
1745 	io_clrsetbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel),  in flexclkgen_config_channel()
1755 	io_clrsetbits32(rcc_base + RCC_XBAR0CFGR + (0x4 * channel),  in flexclkgen_config_channel()
2270 		io_clrsetbits32(rcc_base + RCC_XBAR0CFGR + (channel),  in clk_stm32_flexgen_set_parent()
2390 	io_clrsetbits32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel),  in clk_stm32_flexgen_set_rate()
2400 	io_clrsetbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel),  in clk_stm32_flexgen_set_rate()
3560 		io_clrsetbits32(pdata->rcc_base + RCC_PRIVCFGR(index),  in apply_rcc_rif_config()
3563 		io_clrsetbits32(pdata->rcc_base + RCC_SECCFGR(index),  in apply_rcc_rif_config()
3578 		io_clrsetbits32(pdata->rcc_base + RCC_CIDCFGR(i),  in apply_rcc_rif_config()
3584 		io_clrsetbits32(pdata->rcc_base + RCC_RCFGLOCKR(index),  in apply_rcc_rif_config()