drivers: stm32_risab: implement transient CID0 on AHB errata for RISAB

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compa

drivers: stm32_risab: implement transient CID0 on AHB errata for RISAB

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compartment
filtering is enabled on RISAB3/4/5, this transient CID0 is interpreted
as a fault access by RISAB3/4/5 which aborts current access and returns
an IAC. Described in section 2.3.21 of errata sheet available here: [1].
Therefore, when CID filtering is enabled on RISAB, we must ban CID0 as
a possible CID value configured for any initiator on the bus.
This avoids a conflict between an initiator holding CID0 and the
transient CID0.

Force authorize CID0 access on RISAB so that it can always access
memories protected by RISABs when the "st,errata-ahbrisab" property is
set in the device tree.

Link: https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-device-errata-stmicroelectronics.pdf [1]
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_risab: add .set_memory_conf ops

Add the .set_memory_conf ops to be able to reconfigure memory regions
protected by RISABs dynamically.

Factorize the RIF configuration application.

S

drivers: stm32_risab: add .set_memory_conf ops

Add the .set_memory_conf ops to be able to reconfigure memory regions
protected by RISABs dynamically.

Factorize the RIF configuration application.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_risab: rework regs_access_granted()

Rework regs_access_granted() to always authorize access to RISAB1/2
that can only be accessed by the Cortex-A35.

Also fix the sequence by isolatin

drivers: stm32_risab: rework regs_access_granted()

Rework regs_access_granted() to always authorize access to RISAB1/2
that can only be accessed by the Cortex-A35.

Also fix the sequence by isolating the case where the CID filtering is
not enabled.

Fixes: c413678c6ca6 ("drivers: stm32_risab: add RISAB internal memory firewall driver")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_risab: add RISAB internal memory firewall driver

This driver implements the RISAB driver. Through RISAB registers, a
trusted compartment, or the compartment to which the page configur

drivers: stm32_risab: add RISAB internal memory firewall driver

This driver implements the RISAB driver. Through RISAB registers, a
trusted compartment, or the compartment to which the page configuration
has been delegated, configures the firewall attributes necessary to
access a page.

Each RISAB is dedicated to a internal memory and can cover 128KBytes of
data, separated in 32 pages of 4 KBytes, containing 8 blocks each.

It is possible to align a RISAB secure and privilege regions
allocations with an ARM Cortex M, which defines in its address space
configurable regions with a 256Bytes granularity. The configuration
would be 512Bytes block-based in order to align the two.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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