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Searched refs:set_rate (Results 1 – 25 of 348) sorted by relevance

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/OK3568_Linux_fs/kernel/arch/arm/mach-omap1/
H A Dclock_data.c113 .set_rate = &omap1_set_sossi_rate,
123 .set_rate = omap1_clk_set_rate_ckctl_arm,
137 .set_rate = omap1_clk_set_rate_ckctl_arm,
217 .set_rate = omap1_clk_set_rate_ckctl_arm,
227 .set_rate = omap1_clk_set_rate_ckctl_arm,
239 .set_rate = &omap1_clk_set_rate_dsp_domain,
269 .set_rate = omap1_clk_set_rate_ckctl_arm,
390 .set_rate = omap1_clk_set_rate_ckctl_arm,
404 .set_rate = omap1_clk_set_rate_ckctl_arm,
424 .set_rate = &omap1_set_uart_rate,
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-ep93xx/
H A Dclock.c36 int (*set_rate)(struct clk *clk, unsigned long rate); member
96 .set_rate = set_keytchclk_rate,
103 .set_rate = set_keytchclk_rate,
118 .set_rate = set_div_rate,
125 .set_rate = set_div_rate,
133 .set_rate = set_i2s_sclk_rate,
141 .set_rate = set_i2s_lrclk_rate,
476 if (clk->set_rate) in clk_set_rate()
477 return clk->set_rate(clk, rate); in clk_set_rate()
/OK3568_Linux_fs/kernel/drivers/clk/ti/
H A Ddpll.c37 .set_rate = &omap3_noncore_dpll_set_rate,
62 .set_rate = &omap3_noncore_dpll_set_rate,
75 .set_rate = &omap3_noncore_dpll_set_rate,
94 .set_rate = &omap2_reprogram_dpllcore,
116 .set_rate = &omap3_noncore_dpll_set_rate,
128 .set_rate = &omap3_dpll5_set_rate,
140 .set_rate = &omap3_dpll4_set_rate,
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-composite.c139 return rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate()
159 rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate_and_parent()
163 rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate_and_parent()
261 if (rate_ops->set_rate) { in __clk_hw_register_composite()
263 clk_composite_ops->set_rate = in __clk_hw_register_composite()
275 if (mux_ops->set_parent && rate_ops->set_rate) in __clk_hw_register_composite()
/OK3568_Linux_fs/kernel/drivers/clk/st/
H A Dclk-flexgen.c177 clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate); in flexgen_set_rate()
178 ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div); in flexgen_set_rate()
180 clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate); in flexgen_set_rate()
181 ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div); in flexgen_set_rate()
195 .set_rate = flexgen_set_rate,
/OK3568_Linux_fs/kernel/drivers/clk/actions/
H A Dowl-composite.c157 .set_rate = owl_comp_div_set_rate,
174 .set_rate = owl_comp_fact_set_rate,
186 .set_rate = owl_comp_fix_fact_set_rate,
/OK3568_Linux_fs/kernel/drivers/sh/clk/
H A Dcpg.c182 .set_rate = sh_clk_div_set_rate,
188 .set_rate = sh_clk_div_set_rate,
315 .set_rate = sh_clk_div_set_rate,
367 .set_rate = sh_clk_div_set_rate,
447 .set_rate = fsidiv_set_rate,
H A Dcore.c490 if (likely(clk->ops && clk->ops->set_rate)) { in clk_set_rate()
491 ret = clk->ops->set_rate(clk, rate); in clk_set_rate()
583 if (likely(clkp->ops->set_rate)) in clks_core_resume()
584 clkp->ops->set_rate(clkp, rate); in clks_core_resume()
/OK3568_Linux_fs/kernel/drivers/clk/mvebu/
H A Dclk-corediv.c203 .set_rate = clk_corediv_set_rate,
219 .set_rate = clk_corediv_set_rate,
232 .set_rate = clk_corediv_set_rate,
244 .set_rate = clk_corediv_set_rate,
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/
H A Dclk-regmap-composite.c169 return rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_regmap_composite_set_rate()
329 if (div_ops->set_rate) { in devm_clk_regmap_register_composite()
331 clk_composite_ops->set_rate = in devm_clk_regmap_register_composite()
356 if (fd_ops->set_rate) { in devm_clk_regmap_register_composite()
358 clk_composite_ops->set_rate = in devm_clk_regmap_register_composite()
/OK3568_Linux_fs/kernel/drivers/clk/mxs/
H A Dclk-div.c57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
67 .set_rate = clk_div_set_rate,
/OK3568_Linux_fs/kernel/drivers/clk/samsung/
H A Dclk-pll.c256 .set_rate = samsung_pll35xx_set_rate,
372 .set_rate = samsung_pll36xx_set_rate,
511 .set_rate = samsung_pll45xx_set_rate,
670 .set_rate = samsung_pll46xx_set_rate,
899 .set_rate = samsung_s3c2410_pll_set_rate,
907 .set_rate = samsung_s3c2410_pll_set_rate,
915 .set_rate = samsung_s3c2410_pll_set_rate,
1051 .set_rate = samsung_pll2550xx_set_rate,
1147 .set_rate = samsung_pll2650x_set_rate,
1241 .set_rate = samsung_pll2650xx_set_rate,
/OK3568_Linux_fs/kernel/arch/sh/kernel/cpu/sh4/
H A Dclock-sh4-202.c81 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) in shoc_clk_init()
133 .set_rate = shoc_clk_set_rate,
/OK3568_Linux_fs/kernel/drivers/clk/ux500/
H A Dclk-prcmu.c197 .set_rate = clk_prcmu_set_rate,
214 .set_rate = clk_prcmu_set_rate,
241 .set_rate = clk_prcmu_set_rate,
/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk-periph.c69 return div_ops->set_rate(div_hw, rate, parent_rate); in clk_periph_set_rate()
134 .set_rate = clk_periph_set_rate,
157 .set_rate = clk_periph_set_rate,
H A Dclk-tegra-super-cclk.c44 return tegra_clk_super_ops.set_rate(hw, rate, parent_rate); in cclk_super_set_rate()
100 .set_rate = cclk_super_set_rate,
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3399.c827 ulong clk_id, ulong set_rate) in rk3399_mmc_set_clk() argument
837 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); in rk3399_mmc_set_clk()
841 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3399_mmc_set_clk()
865 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); in rk3399_mmc_set_clk()
868 src_clk_div = DIV_ROUND_UP(OSC_HZ, set_rate); in rk3399_mmc_set_clk()
913 ulong set_rate) in rk3399_ddr_set_clk() argument
921 switch (set_rate) { in rk3399_ddr_set_clk()
951 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate); in rk3399_ddr_set_clk()
955 return set_rate; in rk3399_ddr_set_clk()
1391 .set_rate = rk3399_clk_set_rate,
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/qcom/
H A Dclk-rcg2.c375 .set_rate = clk_rcg2_set_rate,
386 .set_rate = clk_rcg2_set_floor_rate,
512 .set_rate = clk_edp_pixel_set_rate,
570 .set_rate = clk_byte_set_rate,
640 .set_rate = clk_byte2_set_rate,
731 .set_rate = clk_pixel_set_rate,
818 .set_rate = clk_gfx3d_set_rate,
957 .set_rate = clk_rcg2_shared_set_rate,
1219 .set_rate = clk_rcg2_dp_set_rate,
H A Dclk-alpha-pll.c877 .set_rate = clk_alpha_pll_set_rate,
887 .set_rate = alpha_pll_huayra_set_rate,
897 .set_rate = clk_alpha_pll_hwfsm_set_rate,
992 .set_rate = clk_alpha_pll_postdiv_set_rate,
1236 .set_rate = alpha_pll_fabia_set_rate,
1331 .set_rate = clk_trion_pll_postdiv_set_rate,
1377 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1543 .set_rate = alpha_pll_trion_set_rate,
1554 .set_rate = alpha_pll_trion_set_rate,
1561 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
H A Dclk-rcg.c815 .set_rate = clk_rcg_set_rate,
826 .set_rate = clk_rcg_bypass_set_rate,
837 .set_rate = clk_rcg_bypass2_set_rate,
849 .set_rate = clk_rcg_pixel_set_rate,
861 .set_rate = clk_rcg_esc_set_rate,
873 .set_rate = clk_rcg_lcc_set_rate,
885 .set_rate = clk_dyn_rcg_set_rate,
/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-pllv3.c155 .set_rate = clk_pllv3_set_rate,
210 .set_rate = clk_pllv3_sys_set_rate,
299 .set_rate = clk_pllv3_av_set_rate,
392 .set_rate = clk_pllv3_vf610_set_rate,
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-ddr.c113 .set_rate = rockchip_ddrclk_sip_set_rate,
174 .set_rate = rockchip_ddrclk_sip_set_rate_v2,
/OK3568_Linux_fs/kernel/drivers/clk/at91/
H A Dclk-usb.c156 .set_rate = at91sam9x5_clk_usb_set_rate,
192 .set_rate = at91sam9x5_clk_usb_set_rate,
361 .set_rate = at91rm9200_clk_usb_set_rate,
/OK3568_Linux_fs/u-boot/include/
H A Dgeneric-phy-dp.h71 u8 set_rate : 1; member
/OK3568_Linux_fs/kernel/include/linux/phy/
H A Dphy-dp.h73 u8 set_rate : 1; member

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