xref: /OK3568_Linux_fs/kernel/include/linux/phy/phy-dp.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2019 Cadence Design Systems Inc.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #ifndef __PHY_DP_H_
7*4882a593Smuzhiyun #define __PHY_DP_H_
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/types.h>
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun /**
12*4882a593Smuzhiyun  * struct phy_configure_opts_dp - DisplayPort PHY configuration set
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * This structure is used to represent the configuration state of a
15*4882a593Smuzhiyun  * DisplayPort phy.
16*4882a593Smuzhiyun  */
17*4882a593Smuzhiyun struct phy_configure_opts_dp {
18*4882a593Smuzhiyun 	/**
19*4882a593Smuzhiyun 	 * @link_rate:
20*4882a593Smuzhiyun 	 *
21*4882a593Smuzhiyun 	 * Link Rate, in Mb/s, of the main link.
22*4882a593Smuzhiyun 	 *
23*4882a593Smuzhiyun 	 * Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 Mb/s
24*4882a593Smuzhiyun 	 */
25*4882a593Smuzhiyun 	unsigned int link_rate;
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun 	/**
28*4882a593Smuzhiyun 	 * @lanes:
29*4882a593Smuzhiyun 	 *
30*4882a593Smuzhiyun 	 * Number of active, consecutive, data lanes, starting from
31*4882a593Smuzhiyun 	 * lane 0, used for the transmissions on main link.
32*4882a593Smuzhiyun 	 *
33*4882a593Smuzhiyun 	 * Allowed values: 1, 2, 4
34*4882a593Smuzhiyun 	 */
35*4882a593Smuzhiyun 	unsigned int lanes;
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 	/**
38*4882a593Smuzhiyun 	 * @voltage:
39*4882a593Smuzhiyun 	 *
40*4882a593Smuzhiyun 	 * Voltage swing levels, as specified by DisplayPort specification,
41*4882a593Smuzhiyun 	 * to be used by particular lanes. One value per lane.
42*4882a593Smuzhiyun 	 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
43*4882a593Smuzhiyun 	 *
44*4882a593Smuzhiyun 	 * Maximum value: 3
45*4882a593Smuzhiyun 	 */
46*4882a593Smuzhiyun 	unsigned int voltage[4];
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	/**
49*4882a593Smuzhiyun 	 * @pre:
50*4882a593Smuzhiyun 	 *
51*4882a593Smuzhiyun 	 * Pre-emphasis levels, as specified by DisplayPort specification, to be
52*4882a593Smuzhiyun 	 * used by particular lanes. One value per lane.
53*4882a593Smuzhiyun 	 *
54*4882a593Smuzhiyun 	 * Maximum value: 3
55*4882a593Smuzhiyun 	 */
56*4882a593Smuzhiyun 	unsigned int pre[4];
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	/**
59*4882a593Smuzhiyun 	 * @ssc:
60*4882a593Smuzhiyun 	 *
61*4882a593Smuzhiyun 	 * Flag indicating, whether or not to enable spread-spectrum clocking.
62*4882a593Smuzhiyun 	 *
63*4882a593Smuzhiyun 	 */
64*4882a593Smuzhiyun 	u8 ssc : 1;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	/**
67*4882a593Smuzhiyun 	 * @set_rate:
68*4882a593Smuzhiyun 	 *
69*4882a593Smuzhiyun 	 * Flag indicating, whether or not reconfigure link rate and SSC to
70*4882a593Smuzhiyun 	 * requested values.
71*4882a593Smuzhiyun 	 *
72*4882a593Smuzhiyun 	 */
73*4882a593Smuzhiyun 	u8 set_rate : 1;
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	/**
76*4882a593Smuzhiyun 	 * @set_lanes:
77*4882a593Smuzhiyun 	 *
78*4882a593Smuzhiyun 	 * Flag indicating, whether or not reconfigure lane count to
79*4882a593Smuzhiyun 	 * requested value.
80*4882a593Smuzhiyun 	 *
81*4882a593Smuzhiyun 	 */
82*4882a593Smuzhiyun 	u8 set_lanes : 1;
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	/**
85*4882a593Smuzhiyun 	 * @set_voltages:
86*4882a593Smuzhiyun 	 *
87*4882a593Smuzhiyun 	 * Flag indicating, whether or not reconfigure voltage swing
88*4882a593Smuzhiyun 	 * and pre-emphasis to requested values. Only lanes specified
89*4882a593Smuzhiyun 	 * by "lanes" parameter will be affected.
90*4882a593Smuzhiyun 	 *
91*4882a593Smuzhiyun 	 */
92*4882a593Smuzhiyun 	u8 set_voltages : 1;
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun #endif /* __PHY_DP_H_ */
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