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Searched refs:reg_val (Results 1 – 25 of 421) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/csf/
H A Dmali_kbase_csf_registers.h268 #define GLB_VERSION_PATCH_GET(reg_val) (((reg_val)&GLB_VERSION_PATCH_MASK) >> GLB_VERSION_PATCH_SHI… argument
269 #define GLB_VERSION_PATCH_SET(reg_val, value) \ argument
270 …(((reg_val) & ~GLB_VERSION_PATCH_MASK) | (((value) << GLB_VERSION_PATCH_SHIFT) & GLB_VERSION_PATCH…
273 #define GLB_VERSION_MINOR_GET(reg_val) (((reg_val)&GLB_VERSION_MINOR_MASK) >> GLB_VERSION_MINOR_SHI… argument
274 #define GLB_VERSION_MINOR_SET(reg_val, value) \ argument
275 …(((reg_val) & ~GLB_VERSION_MINOR_MASK) | (((value) << GLB_VERSION_MINOR_SHIFT) & GLB_VERSION_MINOR…
278 #define GLB_VERSION_MAJOR_GET(reg_val) (((reg_val)&GLB_VERSION_MAJOR_MASK) >> GLB_VERSION_MAJOR_SHI… argument
279 #define GLB_VERSION_MAJOR_SET(reg_val, value) \ argument
280 …(((reg_val) & ~GLB_VERSION_MAJOR_MASK) | (((value) << GLB_VERSION_MAJOR_SHIFT) & GLB_VERSION_MAJOR…
285 #define CS_REQ_STATE_GET(reg_val) (((reg_val)&CS_REQ_STATE_MASK) >> CS_REQ_STATE_SHIFT) argument
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_mtl.c23 u32 reg_val; in sxgbe_mtl_init() local
25 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
26 reg_val &= ETS_RST; in sxgbe_mtl_init()
31 reg_val &= ETS_WRR; in sxgbe_mtl_init()
34 reg_val |= ETS_WFQ; in sxgbe_mtl_init()
37 reg_val |= ETS_DWRR; in sxgbe_mtl_init()
40 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
44 reg_val &= RAA_SP; in sxgbe_mtl_init()
47 reg_val |= RAA_WSP; in sxgbe_mtl_init()
50 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
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/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/gpu/
H A Dmali_kbase_gpu_regmap.h247 #define AS_FAULTSTATUS_EXCEPTION_TYPE_GET(reg_val) \ argument
248 (((reg_val)&AS_FAULTSTATUS_EXCEPTION_TYPE_MASK) >> AS_FAULTSTATUS_EXCEPTION_TYPE_SHIFT)
253 #define AS_FAULTSTATUS_ACCESS_TYPE_GET(reg_val) \ argument
254 (((reg_val)&AS_FAULTSTATUS_ACCESS_TYPE_MASK) >> AS_FAULTSTATUS_ACCESS_TYPE_SHIFT)
263 #define AS_FAULTSTATUS_SOURCE_ID_GET(reg_val) \ argument
264 (((reg_val)&AS_FAULTSTATUS_SOURCE_ID_MASK) >> AS_FAULTSTATUS_SOURCE_ID_SHIFT)
269 #define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_GET(reg_val) \ argument
270 (((reg_val)&PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_MASK) >> \
316 #define AS_LOCKADDR_LOCKADDR_SIZE_GET(reg_val) \ argument
317 (((reg_val)&AS_LOCKADDR_LOCKADDR_SIZE_MASK) >> \
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/OK3568_Linux_fs/u-boot/drivers/net/phy/
H A Dmscc.c139 u16 reg_val; in mscc_vsc8531_vsc8541_init_scripts() local
149 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); in mscc_vsc8531_vsc8541_init_scripts()
150 reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_LINKDETCTRL_POS, in mscc_vsc8531_vsc8541_init_scripts()
154 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
163 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in mscc_vsc8531_vsc8541_init_scripts()
164 reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_VGATHRESH100_POS, in mscc_vsc8531_vsc8541_init_scripts()
168 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
177 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in mscc_vsc8531_vsc8541_init_scripts()
178 reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_VGAGAIN10_U_POS, in mscc_vsc8531_vsc8541_init_scripts()
182 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
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/OK3568_Linux_fs/kernel/drivers/input/keyboard/
H A Dimx_keypad.c82 unsigned short reg_val; in imx_keypad_scan_matrix() local
93 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
94 reg_val |= 0xff00; in imx_keypad_scan_matrix()
95 writew(reg_val, keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
97 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
98 reg_val &= ~((keypad->cols_en_mask & 0xff) << 8); in imx_keypad_scan_matrix()
99 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
103 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
104 reg_val |= (keypad->cols_en_mask & 0xff) << 8; in imx_keypad_scan_matrix()
105 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
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/OK3568_Linux_fs/u-boot/drivers/mtd/nand/raw/
H A Darasan_nfc.c267 u32 reg_val; in arasan_nand_select_chip() local
269 reg_val = readl(&arasan_nand_base->memadr_reg2); in arasan_nand_select_chip()
271 reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS0_MASK; in arasan_nand_select_chip()
272 writel(reg_val, &arasan_nand_base->memadr_reg2); in arasan_nand_select_chip()
274 reg_val |= ARASAN_NAND_MEM_ADDR2_CS1_MASK; in arasan_nand_select_chip()
275 writel(reg_val, &arasan_nand_base->memadr_reg2); in arasan_nand_select_chip()
281 u32 reg_val; in arasan_nand_enable_ecc() local
283 reg_val = readl(&arasan_nand_base->cmd_reg); in arasan_nand_enable_ecc()
284 reg_val |= ARASAN_NAND_CMD_ECC_ON_MASK; in arasan_nand_enable_ecc()
286 writel(reg_val, &arasan_nand_base->cmd_reg); in arasan_nand_enable_ecc()
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H A Dtegra_nand.c118 u32 reg_val; in nand_waitfor_cmd_completion() local
129 reg_val = readl(&reg->dma_mst_ctrl); in nand_waitfor_cmd_completion()
137 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE | in nand_waitfor_cmd_completion()
139 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE)) in nand_waitfor_cmd_completion()
208 int reg_val; in nand_dev_ready() local
213 reg_val = readl(&info->reg->status); in nand_dev_ready()
214 if (reg_val & STATUS_RBSY0) in nand_dev_ready()
240 u32 reg_val; in nand_clear_interrupt_status() local
243 reg_val = readl(&reg->isr); in nand_clear_interrupt_status()
244 writel(reg_val, &reg->isr); in nand_clear_interrupt_status()
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/OK3568_Linux_fs/u-boot/drivers/usb/musb-new/
H A Dsunxi.c86 static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val) in USBC_WakeUp_ClearChangeDetect() argument
88 u32 temp = reg_val; in USBC_WakeUp_ClearChangeDetect()
99 u32 reg_val; in USBC_EnableIdPullUp() local
101 reg_val = musb_readl(base, USBC_REG_o_ISCR); in USBC_EnableIdPullUp()
102 reg_val |= (1 << USBC_BP_ISCR_ID_PULLUP_EN); in USBC_EnableIdPullUp()
103 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val); in USBC_EnableIdPullUp()
104 musb_writel(base, USBC_REG_o_ISCR, reg_val); in USBC_EnableIdPullUp()
109 u32 reg_val; in USBC_EnableDpDmPullUp() local
111 reg_val = musb_readl(base, USBC_REG_o_ISCR); in USBC_EnableDpDmPullUp()
112 reg_val |= (1 << USBC_BP_ISCR_DPDM_PULLUP_EN); in USBC_EnableDpDmPullUp()
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/OK3568_Linux_fs/u-boot/drivers/video/tegra124/
H A Dsor.c65 u32 reg_val = tegra_sor_readl(sor, reg); in tegra_sor_write_field() local
66 reg_val &= ~mask; in tegra_sor_write_field()
67 reg_val |= val; in tegra_sor_write_field()
68 tegra_sor_writel(sor, reg, reg_val); in tegra_sor_write_field()
96 u32 reg_val = 0; in tegra_dc_sor_poll_register() local
101 reg_val = tegra_sor_readl(sor, reg); in tegra_dc_sor_poll_register()
102 if (((reg_val & mask) == exp_val)) in tegra_dc_sor_poll_register()
108 reg, reg_val, mask, exp_val); in tegra_dc_sor_poll_register()
116 u32 reg_val; in tegra_dc_sor_set_power_state() local
121 reg_val = pu_pd ? PWR_NORMAL_STATE_PU : in tegra_dc_sor_set_power_state()
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/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c67 u32 reg_val; in mctl_ddr3_reset() local
70 reg_val = readl(&timer->cpu_cfg); in mctl_ddr3_reset()
72 if ((reg_val & CPU_CFG_CHIP_VER_MASK) != in mctl_ddr3_reset()
240 u32 reg_val; in mctl_setup_dram_clock() local
247 reg_val = readl(&ccm->pll5_cfg); in mctl_setup_dram_clock()
248 reg_val &= ~CCM_PLL5_CTRL_M_MASK; /* set M to 0 (x1) */ in mctl_setup_dram_clock()
249 reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */ in mctl_setup_dram_clock()
250 reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */ in mctl_setup_dram_clock()
251 reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */ in mctl_setup_dram_clock()
254 reg_val |= CCM_PLL5_CTRL_P(1); in mctl_setup_dram_clock()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/
H A Ddc_helper.c165 uint32_t reg_val) in dmub_reg_value_burst_set_pack() argument
183 cmd_buf->write_values[offload->reg_seq_count] = reg_val; in dmub_reg_value_burst_set_pack()
248 uint32_t reg_val; in generic_reg_update_ex() local
264 reg_val = dm_read_reg(ctx, addr); in generic_reg_update_ex()
265 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; in generic_reg_update_ex()
266 dm_write_reg(ctx, addr, reg_val); in generic_reg_update_ex()
267 return reg_val; in generic_reg_update_ex()
271 uint32_t addr, uint32_t reg_val, int n, in generic_reg_set_ex() argument
287 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; in generic_reg_set_ex()
291 return dmub_reg_value_burst_set_pack(ctx, addr, reg_val); in generic_reg_set_ex()
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/OK3568_Linux_fs/kernel/drivers/power/supply/
H A Dcw221x_battery.c165 unsigned char reg_val[2] = {0, 0}; in cw_read_word() local
170 ret = i2c_smbus_read_i2c_block_data(client, reg, 2, reg_val); in cw_read_word()
173 temp_val_buff = (reg_val[0] << 8) + reg_val[1]; in cw_read_word()
176 ret = i2c_smbus_read_i2c_block_data(client, reg, 2, reg_val); in cw_read_word()
179 temp_val_second = (reg_val[0] << 8) + reg_val[1]; in cw_read_word()
183 ret = i2c_smbus_read_i2c_block_data(client, reg, 2, reg_val); in cw_read_word()
190 buf[0] = reg_val[0]; in cw_read_word()
191 buf[1] = reg_val[1]; in cw_read_word()
227 unsigned char reg_val = CONFIG_MODE_RESTART; in cw221X_active() local
230 ret = cw_write(cw_bat->client, REG_MODE_CONFIG, &reg_val); in cw221X_active()
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/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/
H A Daf9033_priv.h19 struct reg_val { struct
87 static const struct reg_val ofsm_init[] = {
202 static const struct reg_val tuner_init_tua9001[] = {
246 static const struct reg_val tuner_init_fc0011[] = {
309 static const struct reg_val tuner_init_fc0012[] = {
354 static const struct reg_val tuner_init_mxl5007t[] = {
391 static const struct reg_val tuner_init_tda18218[] = {
427 static const struct reg_val tuner_init_fc2580[] = {
467 static const struct reg_val ofsm_init_it9135_v1[] = {
582 static const struct reg_val tuner_init_it9135_38[] = {
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/allwinner/
H A Dsun4i-emac.c95 unsigned int reg_val; in emac_update_speed() local
98 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
99 reg_val &= ~(0x1 << 8); in emac_update_speed()
101 reg_val |= 1 << 8; in emac_update_speed()
102 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
108 unsigned int reg_val; in emac_update_duplex() local
111 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
112 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex()
114 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex()
115 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
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/OK3568_Linux_fs/kernel/drivers/spi/
H A Dspi-slave-mt27xx.c83 u32 reg_val; in mtk_spi_slave_disable_dma() local
85 reg_val = readl(mdata->base + SPIS_DMA_CFG_REG); in mtk_spi_slave_disable_dma()
86 reg_val &= ~RX_DMA_EN; in mtk_spi_slave_disable_dma()
87 reg_val &= ~TX_DMA_EN; in mtk_spi_slave_disable_dma()
88 writel(reg_val, mdata->base + SPIS_DMA_CFG_REG); in mtk_spi_slave_disable_dma()
93 u32 reg_val; in mtk_spi_slave_disable_xfer() local
95 reg_val = readl(mdata->base + SPIS_CFG_REG); in mtk_spi_slave_disable_xfer()
96 reg_val &= ~SPIS_TX_EN; in mtk_spi_slave_disable_xfer()
97 reg_val &= ~SPIS_RX_EN; in mtk_spi_slave_disable_xfer()
98 writel(reg_val, mdata->base + SPIS_CFG_REG); in mtk_spi_slave_disable_xfer()
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H A Dspi-mt65xx.c183 u32 reg_val; in mtk_spi_reset() local
186 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
187 reg_val |= SPI_CMD_RST; in mtk_spi_reset()
188 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
190 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
191 reg_val &= ~SPI_CMD_RST; in mtk_spi_reset()
192 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
199 u32 reg_val; in mtk_spi_prepare_message() local
207 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_prepare_message()
209 reg_val |= SPI_CMD_CPHA; in mtk_spi_prepare_message()
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/OK3568_Linux_fs/kernel/sound/drivers/opl3/
H A Dopl3_synth.c396 unsigned char reg_val; in snd_opl3_play_note() local
416 reg_val = (unsigned char) note->fnum; in snd_opl3_play_note()
418 opl3->command(opl3, opl3_reg, reg_val); in snd_opl3_play_note()
420 reg_val = 0x00; in snd_opl3_play_note()
423 reg_val |= OPL3_KEYON_BIT; in snd_opl3_play_note()
425 reg_val |= (note->octave << 2) & OPL3_BLOCKNUM_MASK; in snd_opl3_play_note()
427 reg_val |= (unsigned char) (note->fnum >> 8) & OPL3_FNUM_HIGH_MASK; in snd_opl3_play_note()
431 opl3->command(opl3, opl3_reg, reg_val); in snd_opl3_play_note()
444 unsigned char reg_val; in snd_opl3_set_voice() local
470 reg_val = 0x00; in snd_opl3_set_voice()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_vbif.c61 u32 reg_val; in dpu_hw_set_mem_type() local
79 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type()
80 reg_val &= ~(0x7 << bit_off); in dpu_hw_set_mem_type()
81 reg_val |= (value & 0x7) << bit_off; in dpu_hw_set_mem_type()
82 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
89 u32 reg_val; in dpu_hw_set_limit_conf() local
100 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_limit_conf()
101 reg_val &= ~(0xFF << bit_off); in dpu_hw_set_limit_conf()
102 reg_val |= (limit) << bit_off; in dpu_hw_set_limit_conf()
103 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_limit_conf()
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/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/mac_ax/
H A Dhw_seq.c76 u32 reg_val; in mac_set_hwseq_reg() local
81 reg_val = MAC_REG_R32(R_AX_HW_SEQ_0_1); in mac_set_hwseq_reg()
82 reg_val &= ~((u32)B_AX_HW_SEQ0_MSK << B_AX_HW_SEQ0_SH); in mac_set_hwseq_reg()
83 reg_val |= (val << B_AX_HW_SEQ0_SH); in mac_set_hwseq_reg()
84 MAC_REG_W32(R_AX_HW_SEQ_0_1, reg_val); in mac_set_hwseq_reg()
87 reg_val = MAC_REG_R32(R_AX_HW_SEQ_0_1); in mac_set_hwseq_reg()
88 reg_val &= ~((u32)B_AX_HW_SEQ1_MSK << B_AX_HW_SEQ1_SH); in mac_set_hwseq_reg()
89 reg_val |= (val << B_AX_HW_SEQ1_SH); in mac_set_hwseq_reg()
90 MAC_REG_W32(R_AX_HW_SEQ_0_1, reg_val); in mac_set_hwseq_reg()
93 reg_val = MAC_REG_R32(R_AX_HW_SEQ_2_3); in mac_set_hwseq_reg()
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/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/mac_ax/
H A Dhw_seq.c76 u32 reg_val; in mac_set_hwseq_reg() local
81 reg_val = MAC_REG_R32(R_AX_HW_SEQ_0_1); in mac_set_hwseq_reg()
82 reg_val &= ~((u32)B_AX_HW_SEQ0_MSK << B_AX_HW_SEQ0_SH); in mac_set_hwseq_reg()
83 reg_val |= (val << B_AX_HW_SEQ0_SH); in mac_set_hwseq_reg()
84 MAC_REG_W32(R_AX_HW_SEQ_0_1, reg_val); in mac_set_hwseq_reg()
87 reg_val = MAC_REG_R32(R_AX_HW_SEQ_0_1); in mac_set_hwseq_reg()
88 reg_val &= ~((u32)B_AX_HW_SEQ1_MSK << B_AX_HW_SEQ1_SH); in mac_set_hwseq_reg()
89 reg_val |= (val << B_AX_HW_SEQ1_SH); in mac_set_hwseq_reg()
90 MAC_REG_W32(R_AX_HW_SEQ_0_1, reg_val); in mac_set_hwseq_reg()
93 reg_val = MAC_REG_R32(R_AX_HW_SEQ_2_3); in mac_set_hwseq_reg()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_hdcp.c45 u32 reg_val; member
199 u32 reg_val, hdcp_int_status; in msm_hdmi_hdcp_irq() local
203 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_INT_CTRL); in msm_hdmi_hdcp_irq()
204 hdcp_int_status = reg_val & HDCP_INT_STATUS_MASK; in msm_hdmi_hdcp_irq()
210 reg_val |= hdcp_int_status << 1; in msm_hdmi_hdcp_irq()
213 reg_val |= HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK; in msm_hdmi_hdcp_irq()
214 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, reg_val); in msm_hdmi_hdcp_irq()
228 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); in msm_hdmi_hdcp_irq()
230 __func__, reg_val); in msm_hdmi_hdcp_irq()
284 u32 reg_val, failure, nack0; in msm_reset_hdcp_ddc_failures() local
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/cavium/liquidio/
H A Dcn23xx_vf_device.c68 u64 reg_val = octeon_read_csr64(oct, in cn23xx_vf_reset_io_queues() local
70 while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) && in cn23xx_vf_reset_io_queues()
71 !(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) && in cn23xx_vf_reset_io_queues()
73 WRITE_ONCE(reg_val, octeon_read_csr64( in cn23xx_vf_reset_io_queues()
83 WRITE_ONCE(reg_val, READ_ONCE(reg_val) & in cn23xx_vf_reset_io_queues()
86 READ_ONCE(reg_val)); in cn23xx_vf_reset_io_queues()
88 WRITE_ONCE(reg_val, octeon_read_csr64( in cn23xx_vf_reset_io_queues()
90 if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) { in cn23xx_vf_reset_io_queues()
153 u32 reg_val; in cn23xx_vf_setup_global_output_regs() local
160 reg_val = in cn23xx_vf_setup_global_output_regs()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gem/
H A Di915_gem_stolen.c175 u32 reg_val = intel_uncore_read(uncore, in g4x_get_stolen_reserved() local
182 IS_GM45(i915) ? "CTG" : "ELK", reg_val); in g4x_get_stolen_reserved()
184 if ((reg_val & G4X_STOLEN_RESERVED_ENABLE) == 0) in g4x_get_stolen_reserved()
193 reg_val); in g4x_get_stolen_reserved()
195 if (!(reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK)) in g4x_get_stolen_reserved()
198 *base = (reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK) << 16; in g4x_get_stolen_reserved()
200 (reg_val & G4X_STOLEN_RESERVED_ADDR1_MASK) < *base); in g4x_get_stolen_reserved()
210 u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED); in gen6_get_stolen_reserved() local
212 drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = %08x\n", reg_val); in gen6_get_stolen_reserved()
214 if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE)) in gen6_get_stolen_reserved()
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/OK3568_Linux_fs/kernel/arch/mips/pci/
H A Dfixup-malta.c70 unsigned char reg_val; in malta_piix_func0_fixup() local
84 pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, &reg_val); in malta_piix_func0_fixup()
85 if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE) in malta_piix_func0_fixup()
88 pci_irq[PCIA+i] = piixirqmap[reg_val & in malta_piix_func0_fixup()
98 pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, &reg_val); in malta_piix_func0_fixup()
99 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val | in malta_piix_func0_fixup()
109 pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val); in malta_piix_func0_fixup()
110 reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT; in malta_piix_func0_fixup()
111 pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val); in malta_piix_func0_fixup()
124 unsigned char reg_val; in malta_piix_func1_fixup() local
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/OK3568_Linux_fs/kernel/arch/powerpc/platforms/powernv/
H A Dopal-fadump.h83 __be64 reg_val; member
88 u64 reg_val) in opal_fadump_set_regval_regnum() argument
92 regs->gpr[reg_num] = reg_val; in opal_fadump_set_regval_regnum()
98 regs->ctr = reg_val; in opal_fadump_set_regval_regnum()
101 regs->link = reg_val; in opal_fadump_set_regval_regnum()
104 regs->xer = reg_val; in opal_fadump_set_regval_regnum()
107 regs->dar = reg_val; in opal_fadump_set_regval_regnum()
110 regs->dsisr = reg_val; in opal_fadump_set_regval_regnum()
113 regs->nip = reg_val; in opal_fadump_set_regval_regnum()
116 regs->msr = reg_val; in opal_fadump_set_regval_regnum()
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