183 	u32 reg_val;  in mtk_spi_reset()  local
186 	reg_val = readl(mdata->base + SPI_CMD_REG);  in mtk_spi_reset()
187 	reg_val |= SPI_CMD_RST;  in mtk_spi_reset()
188 	writel(reg_val, mdata->base + SPI_CMD_REG);  in mtk_spi_reset()
190 	reg_val = readl(mdata->base + SPI_CMD_REG);  in mtk_spi_reset()
191 	reg_val &= ~SPI_CMD_RST;  in mtk_spi_reset()
192 	writel(reg_val, mdata->base + SPI_CMD_REG);  in mtk_spi_reset()
199 	u32 reg_val;  in mtk_spi_prepare_message()  local
207 	reg_val = readl(mdata->base + SPI_CMD_REG);  in mtk_spi_prepare_message()
209 		reg_val |= SPI_CMD_CPHA;  in mtk_spi_prepare_message()
211 		reg_val &= ~SPI_CMD_CPHA;  in mtk_spi_prepare_message()
213 		reg_val |= SPI_CMD_CPOL;  in mtk_spi_prepare_message()
215 		reg_val &= ~SPI_CMD_CPOL;  in mtk_spi_prepare_message()
219 		reg_val &= ~SPI_CMD_TXMSBF;  in mtk_spi_prepare_message()
220 		reg_val &= ~SPI_CMD_RXMSBF;  in mtk_spi_prepare_message()
222 		reg_val |= SPI_CMD_TXMSBF;  in mtk_spi_prepare_message()
223 		reg_val |= SPI_CMD_RXMSBF;  in mtk_spi_prepare_message()
228 	reg_val &= ~SPI_CMD_TX_ENDIAN;  in mtk_spi_prepare_message()
229 	reg_val &= ~SPI_CMD_RX_ENDIAN;  in mtk_spi_prepare_message()
231 	reg_val |= SPI_CMD_TX_ENDIAN;  in mtk_spi_prepare_message()
232 	reg_val |= SPI_CMD_RX_ENDIAN;  in mtk_spi_prepare_message()
238 			reg_val |= SPI_CMD_CS_POL;  in mtk_spi_prepare_message()
240 			reg_val &= ~SPI_CMD_CS_POL;  in mtk_spi_prepare_message()
243 			reg_val |= SPI_CMD_SAMPLE_SEL;  in mtk_spi_prepare_message()
245 			reg_val &= ~SPI_CMD_SAMPLE_SEL;  in mtk_spi_prepare_message()
249 	reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;  in mtk_spi_prepare_message()
252 	reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);  in mtk_spi_prepare_message()
255 	reg_val &= ~SPI_CMD_DEASSERT;  in mtk_spi_prepare_message()
257 	writel(reg_val, mdata->base + SPI_CMD_REG);  in mtk_spi_prepare_message()
269 	u32 reg_val;  in mtk_spi_set_cs()  local
275 	reg_val = readl(mdata->base + SPI_CMD_REG);  in mtk_spi_set_cs()
277 		reg_val |= SPI_CMD_PAUSE_EN;  in mtk_spi_set_cs()
278 		writel(reg_val, mdata->base + SPI_CMD_REG);  in mtk_spi_set_cs()
280 		reg_val &= ~SPI_CMD_PAUSE_EN;  in mtk_spi_set_cs()
281 		writel(reg_val, mdata->base + SPI_CMD_REG);  in mtk_spi_set_cs()
290 	u32 spi_clk_hz, div, sck_time, cs_time, reg_val;  in mtk_spi_prepare_transfer()  local
303 		reg_val = (((sck_time - 1) & 0xffff)  in mtk_spi_prepare_transfer()
305 		reg_val |= (((sck_time - 1) & 0xffff)  in mtk_spi_prepare_transfer()
307 		writel(reg_val, mdata->base + SPI_CFG2_REG);  in mtk_spi_prepare_transfer()
308 		reg_val = (((cs_time - 1) & 0xffff)  in mtk_spi_prepare_transfer()
310 		reg_val |= (((cs_time - 1) & 0xffff)  in mtk_spi_prepare_transfer()
312 		writel(reg_val, mdata->base + SPI_CFG0_REG);  in mtk_spi_prepare_transfer()
314 		reg_val = (((sck_time - 1) & 0xff)  in mtk_spi_prepare_transfer()
316 		reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);  in mtk_spi_prepare_transfer()
317 		reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);  in mtk_spi_prepare_transfer()
318 		reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);  in mtk_spi_prepare_transfer()
319 		writel(reg_val, mdata->base + SPI_CFG0_REG);  in mtk_spi_prepare_transfer()
322 	reg_val = readl(mdata->base + SPI_CFG1_REG);  in mtk_spi_prepare_transfer()
323 	reg_val &= ~SPI_CFG1_CS_IDLE_MASK;  in mtk_spi_prepare_transfer()
324 	reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);  in mtk_spi_prepare_transfer()
325 	writel(reg_val, mdata->base + SPI_CFG1_REG);  in mtk_spi_prepare_transfer()
330 	u32 packet_size, packet_loop, reg_val;  in mtk_spi_setup_packet()  local
336 	reg_val = readl(mdata->base + SPI_CFG1_REG);  in mtk_spi_setup_packet()
337 	reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);  in mtk_spi_setup_packet()
338 	reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;  in mtk_spi_setup_packet()
339 	reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;  in mtk_spi_setup_packet()
340 	writel(reg_val, mdata->base + SPI_CFG1_REG);  in mtk_spi_setup_packet()
427 	u32 reg_val;  in mtk_spi_fifo_transfer()  local
441 			reg_val = 0;  in mtk_spi_fifo_transfer()
442 			memcpy(&reg_val, xfer->tx_buf + (cnt * 4), remainder);  in mtk_spi_fifo_transfer()
443 			writel(reg_val, mdata->base + SPI_TX_DATA_REG);  in mtk_spi_fifo_transfer()
532 	u32 cmd, reg_val, cnt, remainder, len;  in mtk_spi_interrupt()  local
537 	reg_val = readl(mdata->base + SPI_STATUS0_REG);  in mtk_spi_interrupt()
538 	if (reg_val & MTK_SPI_PAUSE_INT_STATUS)  in mtk_spi_interrupt()
550 				reg_val = readl(mdata->base + SPI_RX_DATA_REG);  in mtk_spi_interrupt()
554 					&reg_val,  in mtk_spi_interrupt()
575 			reg_val = 0;  in mtk_spi_interrupt()
576 			memcpy(&reg_val,  in mtk_spi_interrupt()
579 			writel(reg_val, mdata->base + SPI_TX_DATA_REG);  in mtk_spi_interrupt()