139 	u16	reg_val;  in mscc_vsc8531_vsc8541_init_scripts()  local
149 	reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17);  in mscc_vsc8531_vsc8541_init_scripts()
150 	reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_LINKDETCTRL_POS,  in mscc_vsc8531_vsc8541_init_scripts()
154 	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val);  in mscc_vsc8531_vsc8541_init_scripts()
163 	reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18);  in mscc_vsc8531_vsc8541_init_scripts()
164 	reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_VGATHRESH100_POS,  in mscc_vsc8531_vsc8541_init_scripts()
168 	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val);  in mscc_vsc8531_vsc8541_init_scripts()
177 	reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18);  in mscc_vsc8531_vsc8541_init_scripts()
178 	reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_VGAGAIN10_U_POS,  in mscc_vsc8531_vsc8541_init_scripts()
182 	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val);  in mscc_vsc8531_vsc8541_init_scripts()
183 	reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17);  in mscc_vsc8531_vsc8541_init_scripts()
184 	reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_VGAGAIN10_L_POS,  in mscc_vsc8531_vsc8541_init_scripts()
188 	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val);  in mscc_vsc8531_vsc8541_init_scripts()
248 	u16     reg_val = 0;  in mscc_phy_soft_reset()  local
253 	reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);  in mscc_phy_soft_reset()
254 	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, (reg_val | BMCR_RESET));  in mscc_phy_soft_reset()
256 	reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);  in mscc_phy_soft_reset()
258 	while ((reg_val & BMCR_RESET) && (timeout > 0)) {  in mscc_phy_soft_reset()
259 		reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);  in mscc_phy_soft_reset()
275 	u16	reg_val = 0;  in vsc8531_vsc8541_mac_config()  local
314 	reg_val = phy_read(phydev, MDIO_DEVAD_NONE,  in vsc8531_vsc8541_mac_config()
317 	reg_val = bitfield_replace(reg_val, MAC_IF_SELECTION_POS,  in vsc8531_vsc8541_mac_config()
321 		  MSCC_PHY_EXT_PHY_CNTL_1_REG, reg_val);  in vsc8531_vsc8541_mac_config()
326 	reg_val = phy_read(phydev, MDIO_DEVAD_NONE,  in vsc8531_vsc8541_mac_config()
328 	reg_val = bitfield_replace(reg_val, RX_CLK_OUT_POS,  in vsc8531_vsc8541_mac_config()
332 		  MSCC_PHY_RGMII_CNTL_REG, reg_val);  in vsc8531_vsc8541_mac_config()
343 	u16  reg_val;  in vsc8531_config()  local
374 	reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG);  in vsc8531_config()
377 	reg_val = bitfield_replace(reg_val, RGMII_RX_CLK_DELAY_POS,  in vsc8531_config()
380 	reg_val = bitfield_replace(reg_val, RGMII_TX_CLK_DELAY_POS,  in vsc8531_config()
383 	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg_val);  in vsc8531_config()
385 	reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL);  in vsc8531_config()
387 	reg_val = bitfield_replace(reg_val, EDGE_RATE_CNTL_POS,  in vsc8531_config()
390 	reg_val = bitfield_replace(reg_val, RMII_CLK_OUT_ENABLE_POS,  in vsc8531_config()
393 	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL, reg_val);  in vsc8531_config()
403 	u16  reg_val;  in vsc8541_config()  local
436 	reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG);  in vsc8541_config()
438 	reg_val = bitfield_replace(reg_val, RGMII_RX_CLK_DELAY_POS,  in vsc8541_config()
441 	reg_val = bitfield_replace(reg_val, RGMII_TX_CLK_DELAY_POS,  in vsc8541_config()
443 	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg_val);  in vsc8541_config()
445 	reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL);  in vsc8541_config()
447 	reg_val = bitfield_replace(reg_val, EDGE_RATE_CNTL_POS,  in vsc8541_config()
450 	reg_val = bitfield_replace(reg_val, RMII_CLK_OUT_ENABLE_POS,  in vsc8541_config()
453 	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL, reg_val);  in vsc8541_config()