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Searched refs:pll_config (Results 1 – 15 of 15) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/video/
H A Dssd2828.c278 static u32 decode_pll_config(u32 pll_config, u32 reference_freq_khz) in decode_pll_config() argument
280 u32 mul_factor = pll_config & 0xFF; in decode_pll_config()
281 u32 div_factor = (pll_config >> 8) & 0x1F; in decode_pll_config()
343 u32 lp_div, pll_freq_kbps, reference_freq_khz, pll_config; in ssd2828_init() local
405 pll_config = construct_pll_config( in ssd2828_init()
408 write_hw_register(cfg, SSD2828_PLCR, pll_config); in ssd2828_init()
410 pll_freq_kbps = decode_pll_config(pll_config, reference_freq_khz); in ssd2828_init()
/OK3568_Linux_fs/kernel/drivers/clk/qcom/
H A Dclk-pll.h61 struct pll_config { struct
77 const struct pll_config *config, bool fsm_mode); argument
79 const struct pll_config *config, bool fsm_mode);
H A Dclk-pll.c219 const struct pll_config *config) in clk_pll_configure()
246 const struct pll_config *config, bool fsm_mode) in clk_pll_configure_sr()
255 const struct pll_config *config, bool fsm_mode) in clk_pll_configure_sr_hpm_lp()
H A Dlcc-ipq806x.c42 static const struct pll_config pll4_config = {
H A Dmmcc-msm8974.c2295 static const struct pll_config mmpll1_config = {
2309 static struct pll_config mmpll3_config = {
H A Dmmcc-apq8084.c3028 static const struct pll_config mmpll1_config = {
3042 static const struct pll_config mmpll3_config = {
H A Dgcc-msm8939.c209 static const struct pll_config gpll3_config = {
256 static struct pll_config gpll4_config = {
H A Dmmcc-msm8960.c140 static const struct pll_config pll15_config = {
/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_ti814x.c224 static void pll_config(u32 base, u32 n, u32 m, u32 m2, in pll_config() function
309 pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0); in mpu_pll_config()
324 pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1); in l3_pll_config()
329 pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1); in ddr_pll_config()
/OK3568_Linux_fs/kernel/drivers/net/wireless/rsi/
H A Drsi_boot_params.h77 struct pll_config { struct
122 struct pll_config pll_config_g;
/OK3568_Linux_fs/u-boot/drivers/clk/renesas/
H A Dclk-rcar-gen3.c794 const struct rcar_gen3_cpg_pll_config *pll_config = in gen3_clk_get_rate() local
837 rate = gen3_clk_get_rate(&parent) / pll_config->extal_div; in gen3_clk_get_rate()
840 core->parent, pll_config->extal_div, rate); in gen3_clk_get_rate()
852 rate = gen3_clk_get_rate(&parent) * pll_config->pll1_mult; in gen3_clk_get_rate()
855 core->parent, pll_config->pll1_mult, rate); in gen3_clk_get_rate()
867 rate = gen3_clk_get_rate(&parent) * pll_config->pll3_mult; in gen3_clk_get_rate()
870 core->parent, pll_config->pll3_mult, rate); in gen3_clk_get_rate()
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c872 struct pll_div pll_config = {0}; in rk3368_armclk_set_clk() local
889 ret = pll_para_config(hz, &pll_config, &pll_div); in rk3368_armclk_set_clk()
904 ret = rkclk_set_pll(priv->cru, pll_id, &pll_config); in rk3368_armclk_set_clk()
922 ret = rkclk_set_pll(priv->cru, pll_id, &pll_config); in rk3368_armclk_set_clk()
1000 struct pll_div pll_config = {0}; in rk3368_clk_set_rate() local
1010 ret = pll_para_config(rate, &pll_config, &pll_div); in rk3368_clk_set_rate()
1014 ret = rkclk_set_pll(priv->cru, clk->id - 1, &pll_config); in rk3368_clk_set_rate()
/OK3568_Linux_fs/kernel/drivers/net/wireless/ti/wl12xx/
H A Dmain.c866 u16 pll_config; in wl128x_configure_mcs_pll() local
891 ret = wl12xx_top_reg_read(wl, MCS_PLL_CONFIG_REG, &pll_config); in wl128x_configure_mcs_pll()
895 if (pll_config == 0xFFFF) in wl128x_configure_mcs_pll()
897 pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT); in wl128x_configure_mcs_pll()
898 pll_config |= MCS_PLL_ENABLE_HP; in wl128x_configure_mcs_pll()
899 ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config); in wl128x_configure_mcs_pll()
/OK3568_Linux_fs/u-boot/doc/
H A DREADME.socfpga131 pll_config.h
143 -rw-r--r-- 1 sarnold sarnold 3190 Mar 21 18:11 pll_config.h
/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/
H A Dqts-filter.sh120 ${in_bsp_dir}/generated/pll_config.h |