1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __QCOM_CLK_PLL_H__ 7*4882a593Smuzhiyun #define __QCOM_CLK_PLL_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/clk-provider.h> 10*4882a593Smuzhiyun #include "clk-regmap.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /** 13*4882a593Smuzhiyun * struct pll_freq_tbl - PLL frequency table 14*4882a593Smuzhiyun * @l: L value 15*4882a593Smuzhiyun * @m: M value 16*4882a593Smuzhiyun * @n: N value 17*4882a593Smuzhiyun * @ibits: internal values 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun struct pll_freq_tbl { 20*4882a593Smuzhiyun unsigned long freq; 21*4882a593Smuzhiyun u16 l; 22*4882a593Smuzhiyun u16 m; 23*4882a593Smuzhiyun u16 n; 24*4882a593Smuzhiyun u32 ibits; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /** 28*4882a593Smuzhiyun * struct clk_pll - phase locked loop (PLL) 29*4882a593Smuzhiyun * @l_reg: L register 30*4882a593Smuzhiyun * @m_reg: M register 31*4882a593Smuzhiyun * @n_reg: N register 32*4882a593Smuzhiyun * @config_reg: config register 33*4882a593Smuzhiyun * @mode_reg: mode register 34*4882a593Smuzhiyun * @status_reg: status register 35*4882a593Smuzhiyun * @status_bit: ANDed with @status_reg to determine if PLL is enabled 36*4882a593Smuzhiyun * @freq_tbl: PLL frequency table 37*4882a593Smuzhiyun * @hw: handle between common and hardware-specific interfaces 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun struct clk_pll { 40*4882a593Smuzhiyun u32 l_reg; 41*4882a593Smuzhiyun u32 m_reg; 42*4882a593Smuzhiyun u32 n_reg; 43*4882a593Smuzhiyun u32 config_reg; 44*4882a593Smuzhiyun u32 mode_reg; 45*4882a593Smuzhiyun u32 status_reg; 46*4882a593Smuzhiyun u8 status_bit; 47*4882a593Smuzhiyun u8 post_div_width; 48*4882a593Smuzhiyun u8 post_div_shift; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun const struct pll_freq_tbl *freq_tbl; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct clk_regmap clkr; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun extern const struct clk_ops clk_pll_ops; 56*4882a593Smuzhiyun extern const struct clk_ops clk_pll_vote_ops; 57*4882a593Smuzhiyun extern const struct clk_ops clk_pll_sr2_ops; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun struct pll_config { 62*4882a593Smuzhiyun u16 l; 63*4882a593Smuzhiyun u32 m; 64*4882a593Smuzhiyun u32 n; 65*4882a593Smuzhiyun u32 vco_val; 66*4882a593Smuzhiyun u32 vco_mask; 67*4882a593Smuzhiyun u32 pre_div_val; 68*4882a593Smuzhiyun u32 pre_div_mask; 69*4882a593Smuzhiyun u32 post_div_val; 70*4882a593Smuzhiyun u32 post_div_mask; 71*4882a593Smuzhiyun u32 mn_ena_mask; 72*4882a593Smuzhiyun u32 main_output_mask; 73*4882a593Smuzhiyun u32 aux_output_mask; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap, 77*4882a593Smuzhiyun const struct pll_config *config, bool fsm_mode); 78*4882a593Smuzhiyun void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, 79*4882a593Smuzhiyun const struct pll_config *config, bool fsm_mode); 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #endif 82