| /OK3568_Linux_fs/kernel/drivers/clk/zynqmp/ |
| H A D | pll.c | 101 u32 fbdiv; in zynqmp_pll_round_rate() local
114 fbdiv = DIV_ROUND_CLOSEST(rate, *prate); in zynqmp_pll_round_rate()
115 if (fbdiv < PLL_FBDIV_MIN || fbdiv > PLL_FBDIV_MAX) { in zynqmp_pll_round_rate()
116 fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); in zynqmp_pll_round_rate()
117 rate = *prate * fbdiv; in zynqmp_pll_round_rate()
136 u32 fbdiv, data; in zynqmp_pll_recalc_rate() local
141 ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv); in zynqmp_pll_recalc_rate()
146 rate = parent_rate * fbdiv; in zynqmp_pll_recalc_rate()
173 u32 fbdiv; in zynqmp_pll_set_rate() local
199 fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate); in zynqmp_pll_set_rate()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/clk/zynq/ |
| H A D | pll.c | 54 u32 fbdiv; in zynq_pll_round_rate() local
56 fbdiv = DIV_ROUND_CLOSEST(rate, *prate); in zynq_pll_round_rate()
57 if (fbdiv < PLL_FBDIV_MIN) in zynq_pll_round_rate()
58 fbdiv = PLL_FBDIV_MIN; in zynq_pll_round_rate()
59 else if (fbdiv > PLL_FBDIV_MAX) in zynq_pll_round_rate()
60 fbdiv = PLL_FBDIV_MAX; in zynq_pll_round_rate()
62 return *prate * fbdiv; in zynq_pll_round_rate()
75 u32 fbdiv; in zynq_pll_recalc_rate() local
81 fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >> in zynq_pll_recalc_rate()
84 return parent_rate * fbdiv; in zynq_pll_recalc_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/analogbits/ |
| H A D | wrpll-cln28hpc.c | 227 u8 fbdiv, divq, best_r, r; in wrpll_configure_for_rate() local
263 fbdiv = __wrpll_calc_fbdiv(c); in wrpll_configure_for_rate()
275 f >>= (fbdiv - 1); in wrpll_configure_for_rate()
278 vco_pre = fbdiv * post_divr_freq; in wrpll_configure_for_rate()
333 u8 fbdiv; in wrpll_calc_output_rate() local
341 fbdiv = __wrpll_calc_fbdiv(c); in wrpll_calc_output_rate()
342 n = parent_rate * fbdiv * (c->divf + 1); in wrpll_calc_output_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/ |
| H A D | clk-regmap-pll.c | 69 unsigned int postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass; in clk_regmap_pll_recalc_rate() local
79 fbdiv = (con0 & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in clk_regmap_pll_recalc_rate()
88 foutvco = prate * fbdiv; in clk_regmap_pll_recalc_rate()
106 u8 *refdiv, u16 *fbdiv, in clk_pll_round_rate() argument
216 if (fbdiv) in clk_pll_round_rate()
217 *fbdiv = _fbdiv; in clk_pll_round_rate()
254 u16 fbdiv; in clk_regmap_pll_set_rate() local
258 rate = clk_pll_round_rate(prate, drate, &refdiv, &fbdiv, &postdiv1, in clk_regmap_pll_set_rate()
272 PLL_FBDIV(fbdiv)); in clk_regmap_pll_set_rate()
280 refdiv, fbdiv, frac); in clk_regmap_pll_set_rate()
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| /OK3568_Linux_fs/kernel/drivers/misc/rk628/ |
| H A D | rk628_cru.c | 63 u32 postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass; in rk628_cru_clk_get_rate_pll() local
91 fbdiv = (con0 & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rk628_cru_clk_get_rate_pll()
100 foutvco = parent_rate * fbdiv; in rk628_cru_clk_get_rate_pll()
124 u16 fbdiv = 0; in rk628_cru_clk_set_rate_pll() local
194 fbdiv = tmp; in rk628_cru_clk_set_rate_pll()
195 if (fbdiv < 10 || fbdiv > 1600) in rk628_cru_clk_set_rate_pll()
198 tmp = (u64)fbdiv * fin; in rk628_cru_clk_set_rate_pll()
225 foutvco = fin * fbdiv; in rk628_cru_clk_set_rate_pll()
241 PLL_FBDIV(fbdiv)); in rk628_cru_clk_set_rate_pll()
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| /OK3568_Linux_fs/kernel/drivers/clk/pistachio/ |
| H A D | clk-pll.c | 211 vco *= (params->fbdiv << 24) + params->frac; in pll_gf40lp_frac_set_rate()
230 (params->fbdiv << PLL_CTRL1_FBDIV_SHIFT); in pll_gf40lp_frac_set_rate()
273 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; in pll_gf40lp_frac_recalc_rate() local
277 fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK; in pll_gf40lp_frac_recalc_rate()
289 rate *= (fbdiv << 24) + frac; in pll_gf40lp_frac_recalc_rate()
291 rate *= (fbdiv << 24); in pll_gf40lp_frac_recalc_rate()
366 vco = div_u64(params->fref * params->fbdiv, params->refdiv); in pll_gf40lp_laint_set_rate()
398 (params->fbdiv << PLL_CTRL1_FBDIV_SHIFT) | in pll_gf40lp_laint_set_rate()
413 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
418 fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK; in pll_gf40lp_laint_recalc_rate()
[all …]
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| /OK3568_Linux_fs/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3399.c | 37 u32 fbdiv; member
50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
344 u32 refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
354 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rkclk_pll_get_rate()
359 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
369 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
374 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
378 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
392 div->fbdiv << PLL_FBDIV_SHIFT); in rkclk_set_pll()
447 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_para_config() local
[all …]
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| H A D | clk_pll.c | 133 rate_table->fbdiv = foutvco / clk_gcd; in rockchip_pll_clk_set_by_auto()
141 rate_table->fbdiv, rate_table->postdiv1, in rockchip_pll_clk_set_by_auto()
150 rate_table->fbdiv = foutvco / MHZ / clk_gcd; in rockchip_pll_clk_set_by_auto()
152 rate_table->refdiv, rate_table->fbdiv); in rockchip_pll_clk_set_by_auto()
262 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv); in rk3036_pll_set_rate()
284 rate->fbdiv); in rk3036_pll_set_rate()
330 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; in rk3036_pll_get_rate() local
352 fbdiv = (con & RK3036_PLLCON0_FBDIV_MASK) >> in rk3036_pll_get_rate()
364 rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rk3036_pll_get_rate()
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| H A D | clk_rk3036.c | 51 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
69 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
74 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
87 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
204 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
231 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rkclk_pll_get_rate()
235 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
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| /OK3568_Linux_fs/u-boot/drivers/video/drm/ |
| H A D | inno_video_combo_phy.c | 311 u16 fbdiv; member
404 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8)); in inno_mipi_dphy_max_2_5GHz_pll_enable()
406 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); in inno_mipi_dphy_max_2_5GHz_pll_enable()
423 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8)); in inno_mipi_dphy_max_1GHz_pll_enable()
425 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); in inno_mipi_dphy_max_1GHz_pll_enable()
630 u16 fbdiv = 28; in inno_video_phy_lvds_mode_enable() local
656 REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv >> 8)); in inno_video_phy_lvds_mode_enable()
658 REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv)); in inno_video_phy_lvds_mode_enable()
766 u8 *prediv, u16 *fbdiv) in inno_video_phy_pll_round_rate() argument
827 *fbdiv = best_fbdiv; in inno_video_phy_pll_round_rate()
[all …]
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| H A D | rockchip-inno-hdmi-phy.c | 179 u16 fbdiv; member
194 u16 fbdiv; member
592 v = POST_PLL_FB_DIV_8(cfg->fbdiv >> 8); in inno_hdmi_phy_rk3228_power_on()
594 inno_write(inno, 0xea, POST_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_power_on()
668 v = PRE_PLL_FB_DIV_8(cfg->fbdiv >> 8) | in inno_hdmi_phy_rk3228_pre_pll_update()
672 inno_write(inno, 0xe3, PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_pre_pll_update()
731 val = cfg->fbdiv & 0xff; in inno_hdmi_phy_rk3328_power_on()
735 val = (cfg->fbdiv >> 8) | cfg->prediv; in inno_hdmi_phy_rk3328_power_on()
740 val = (cfg->fbdiv >> 8) | cfg->prediv; in inno_hdmi_phy_rk3328_power_on()
831 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0; in inno_hdmi_phy_rk3328_pre_pll_update()
[all …]
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| H A D | samsung_mipi_dcphy.c | 196 u16 fbdiv; member
1301 phy_update_bits(samsung, PLL_CON2, M_MASK, M(samsung->pll.fbdiv)); in samsung_mipi_dcphy_pll_configure()
1609 u16 fbdiv = samsung->pll.fbdiv; in samsung_mipi_dcphy_pll_ssc_modulation_calc() local
1624 mr = DIV_ROUND_UP(_mfr * _mrr * 100, fbdiv << 6); in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1651 u8 *prediv, u16 *fbdiv, int *dsm, u8 *scaler) in samsung_mipi_dcphy_pll_round_rate() argument
1723 *fbdiv = best_fbdiv; in samsung_mipi_dcphy_pll_round_rate()
1738 u16 fbdiv = 1; in samsung_mipi_dcphy_set_pll() local
1745 &fbdiv, &dsm, &scaler); in samsung_mipi_dcphy_set_pll()
1748 dev_info(samsung->dev, "fout=%lu, prediv=%u, fbdiv=%u\n", fout, prediv, fbdiv); in samsung_mipi_dcphy_set_pll()
1751 samsung->pll.fbdiv = fbdiv; in samsung_mipi_dcphy_set_pll()
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| H A D | rk618_dsi.c | 214 u16 fbdiv; member
298 u32 fout, fref, prediv, fbdiv; in rk618_dsi_set_hs_clk() local
336 fbdiv = tmp; in rk618_dsi_set_hs_clk()
338 if (fbdiv < 12 || fbdiv > 511) in rk618_dsi_set_hs_clk()
341 if (fbdiv == 15) in rk618_dsi_set_hs_clk()
344 tmp = (u64)fbdiv * fref; in rk618_dsi_set_hs_clk()
351 phy->fbdiv = fbdiv; in rk618_dsi_set_hs_clk()
356 phy->fbdiv = fbdiv; in rk618_dsi_set_hs_clk()
400 REG_PREDIV_MASK, REG_FBDIV_HI(phy->fbdiv >> 8) | in rk618_dsi_phy_power_on()
403 REG_FBDIV_LO_MASK, REG_FBDIV_LO(phy->fbdiv)); in rk618_dsi_phy_power_on()
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| /OK3568_Linux_fs/kernel/drivers/clk/axs10x/ |
| H A D | i2s_pll_clock.c | 30 unsigned int fbdiv; member
105 unsigned int idiv, fbdiv, odiv; in i2s_pll_recalc_rate() local
108 fbdiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_FBDIV_REG)); in i2s_pll_recalc_rate()
111 return ((parent_rate / idiv) * fbdiv) / odiv; in i2s_pll_recalc_rate()
148 i2s_pll_write(clk, PLL_FBDIV_REG, pll_cfg[i].fbdiv); in i2s_pll_set_rate()
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| H A D | pll_clock.c | 73 u32 fbdiv; member
143 u32 idiv, fbdiv, odiv; in axs10x_pll_recalc_rate() local
147 fbdiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_FBDIV)); in axs10x_pll_recalc_rate()
150 rate = (u64)parent_rate * fbdiv; in axs10x_pll_recalc_rate()
189 axs10x_encode_div(pll_cfg[i].fbdiv, 0)); in axs10x_pll_set_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/mmp/ |
| H A D | clk-pll.c | 49 u32 fbdiv, refdiv, postdiv; in mmp_clk_pll_recalc_rate() local
59 fbdiv = (val >> pll->shift) & 0x1ff; in mmp_clk_pll_recalc_rate()
62 fbdiv = 2; in mmp_clk_pll_recalc_rate()
74 rate *= 2 * fbdiv; in mmp_clk_pll_recalc_rate()
88 rate *= fbdiv + 2; in mmp_clk_pll_recalc_rate()
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| /OK3568_Linux_fs/kernel/drivers/media/i2c/rk628/ |
| H A D | rk628_cru.c | 64 u32 postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass; in rk628_cru_clk_get_rate_pll() local
92 fbdiv = (con0 & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rk628_cru_clk_get_rate_pll()
101 foutvco = parent_rate * fbdiv; in rk628_cru_clk_get_rate_pll()
125 u16 fbdiv = 0; in rk628_cru_clk_set_rate_pll() local
200 fbdiv = tmp; in rk628_cru_clk_set_rate_pll()
201 if (fbdiv < 10 || fbdiv > 1600) in rk628_cru_clk_set_rate_pll()
204 tmp = (u64)fbdiv * fin; in rk628_cru_clk_set_rate_pll()
231 foutvco = fin * fbdiv; in rk628_cru_clk_set_rate_pll()
247 PLL_FBDIV(fbdiv)); in rk628_cru_clk_set_rate_pll()
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| /OK3568_Linux_fs/kernel/drivers/phy/rockchip/ |
| H A D | phy-rockchip-inno-video-combo-phy.c | 214 u16 fbdiv; member
321 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8)); in inno_video_phy_mipi_mode_enable()
323 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); in inno_video_phy_mipi_mode_enable()
450 u16 fbdiv = 28; in inno_video_phy_lvds_mode_enable() local
466 REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv >> 8)); in inno_video_phy_lvds_mode_enable()
468 REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv)); in inno_video_phy_lvds_mode_enable()
602 u8 *prediv, u16 *fbdiv) in inno_video_phy_pll_round_rate() argument
663 *fbdiv = best_fbdiv; in inno_video_phy_pll_round_rate()
676 u16 fbdiv = 1; in inno_video_phy_pll_clk_round_rate() local
680 &prediv, &fbdiv); in inno_video_phy_pll_clk_round_rate()
[all …]
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| H A D | phy-rockchip-inno-hdmi-phy.c | 194 u16 fbdiv; member
209 u16 fbdiv; member
733 v = POST_PLL_FB_DIV_8(cfg->fbdiv >> 8); in inno_hdmi_phy_rk3228_power_on()
735 inno_write(inno, 0xea, POST_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_power_on()
853 v = PRE_PLL_FB_DIV_8(cfg->fbdiv >> 8) | in inno_hdmi_phy_rk3228_pre_pll_update()
857 inno_write(inno, 0xe3, PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_pre_pll_update()
907 val = cfg->fbdiv & 0xff; in inno_hdmi_phy_rk3328_power_on()
911 val = (cfg->fbdiv >> 8) | cfg->prediv; in inno_hdmi_phy_rk3328_power_on()
916 val = (cfg->fbdiv >> 8) | cfg->prediv; in inno_hdmi_phy_rk3328_power_on()
1035 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0; in inno_hdmi_phy_rk3328_pre_pll_update()
[all …]
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| H A D | phy-rockchip-inno-mipi-dphy.c | 233 u16 fbdiv; member
356 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8)); in inno_mipi_dphy_pll_enable()
358 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); in inno_mipi_dphy_pll_enable()
521 u8 *prediv, u16 *fbdiv) in inno_mipi_dphy_pll_round_rate() argument
573 *fbdiv = best_fbdiv; in inno_mipi_dphy_pll_round_rate()
623 u16 fbdiv = 1; in inno_mipi_dphy_pll_clk_round_rate() local
627 &prediv, &fbdiv); in inno_mipi_dphy_pll_clk_round_rate()
632 __func__, fout, prediv, fbdiv); in inno_mipi_dphy_pll_clk_round_rate()
635 inno->pll.fbdiv = fbdiv; in inno_mipi_dphy_pll_clk_round_rate()
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| /OK3568_Linux_fs/u-boot/drivers/video/rockchip/ |
| H A D | rk_mipi.c | 203 u64 fbdiv; in rk_mipi_phy_enable() local
281 fbdiv = ddr_clk * prediv / refclk; in rk_mipi_phy_enable()
282 ddr_clk = refclk * fbdiv / prediv; in rk_mipi_phy_enable()
286 __func__, refclk, prediv, fbdiv, ddr_clk); in rk_mipi_phy_enable()
291 test_data[0] = (fbdiv - 1) & 0x1f; in rk_mipi_phy_enable()
293 test_data[0] = (fbdiv - 1) >> 5 | 0x80; in rk_mipi_phy_enable()
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| /OK3568_Linux_fs/kernel/drivers/clk/rockchip/ |
| H A D | clk-pll.c | 223 rate_table->fbdiv = foutvco / clk_gcd; in rockchip_pll_clk_set_by_auto()
229 rate_table->fbdiv, rate_table->postdiv1, in rockchip_pll_clk_set_by_auto()
240 rate_table->fbdiv = foutvco / MHZ / clk_gcd; in rockchip_pll_clk_set_by_auto()
242 rate_table->refdiv, rate_table->fbdiv); in rockchip_pll_clk_set_by_auto()
490 unsigned int fbdiv, postdiv1, refdiv, postdiv2; in rockchip_rk3036_pll_con_to_rate() local
493 fbdiv = ((con0 >> RK3036_PLLCON0_FBDIV_SHIFT) & in rockchip_rk3036_pll_con_to_rate()
502 rate64 *= fbdiv; in rockchip_rk3036_pll_con_to_rate()
516 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) in rockchip_rk3036_pll_get_params()
546 rate64 *= cur.fbdiv; in rockchip_rk3036_pll_recalc_rate()
575 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3036_pll_set_params()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/clk/berlin/ |
| H A D | berlin2-pll.c | 46 u32 val, fbdiv, rfdiv, vcodivsel, vcodiv; in berlin2_pll_recalc_rate() local
50 fbdiv = (val >> map->fbdiv_shift) & FBDIV_MASK; in berlin2_pll_recalc_rate()
66 rate *= fbdiv * map->mult; in berlin2_pll_recalc_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/ |
| H A D | clk-hsdk-pll.c | 53 u32 fbdiv; member
146 val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT; in hsdk_pll_set_cfg()
176 u32 idiv, fbdiv, odiv; in hsdk_pll_recalc_rate() local
194 fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT)); in hsdk_pll_recalc_rate()
198 rate = (u64)parent_rate * fbdiv; in hsdk_pll_recalc_rate()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/rk618/ |
| H A D | rk618_dsi.c | 221 u16 fbdiv; member
287 u32 fout, fref, prediv, fbdiv; in rk618_dsi_set_hs_clk() local
320 fbdiv = tmp; in rk618_dsi_set_hs_clk()
322 if (fbdiv < 12 || fbdiv > 511) in rk618_dsi_set_hs_clk()
325 if (fbdiv == 15) in rk618_dsi_set_hs_clk()
328 tmp = (u64)fbdiv * fref; in rk618_dsi_set_hs_clk()
335 phy->fbdiv = fbdiv; in rk618_dsi_set_hs_clk()
340 phy->fbdiv = fbdiv; in rk618_dsi_set_hs_clk()
387 REG_PREDIV_MASK, REG_FBDIV_HI(phy->fbdiv >> 8) | in rk618_dsi_phy_power_on()
390 REG_FBDIV_LO_MASK, REG_FBDIV_LO(phy->fbdiv)); in rk618_dsi_phy_power_on()
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