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Searched refs:clksel (Results 1 – 17 of 17) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Ddw_mmc-exynos.c133 u32 clksel; in dw_mci_exynos_set_clksel_timing() local
137 clksel = mci_readl(host, CLKSEL64); in dw_mci_exynos_set_clksel_timing()
139 clksel = mci_readl(host, CLKSEL); in dw_mci_exynos_set_clksel_timing()
141 clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; in dw_mci_exynos_set_clksel_timing()
145 mci_writel(host, CLKSEL64, clksel); in dw_mci_exynos_set_clksel_timing()
147 mci_writel(host, CLKSEL, clksel); in dw_mci_exynos_set_clksel_timing()
156 if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->slot) in dw_mci_exynos_set_clksel_timing()
205 u32 clksel; in dw_mci_exynos_resume_noirq() local
214 clksel = mci_readl(host, CLKSEL64); in dw_mci_exynos_resume_noirq()
216 clksel = mci_readl(host, CLKSEL); in dw_mci_exynos_resume_noirq()
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H A Ddw_mmc-zx.c38 unsigned int clksel; in dw_mci_zx_emmc_set_delay() local
54 ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG1, &clksel); in dw_mci_zx_emmc_set_delay()
59 clksel &= ~CLK_SAMP_DELAY_MASK; in dw_mci_zx_emmc_set_delay()
60 clksel |= CLK_SAMP_DELAY(delay); in dw_mci_zx_emmc_set_delay()
62 clksel &= ~READ_DQS_DELAY_MASK; in dw_mci_zx_emmc_set_delay()
63 clksel |= READ_DQS_DELAY(delay); in dw_mci_zx_emmc_set_delay()
66 regmap_write(sysc_base, LB_AON_EMMC_CFG_REG1, clksel); in dw_mci_zx_emmc_set_delay()
74 ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG2, &clksel); in dw_mci_zx_emmc_set_delay()
78 } while (--loop && !(clksel & ZX_DLL_LOCKED)); in dw_mci_zx_emmc_set_delay()
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-cpu.c110 const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; in rockchip_cpuclk_set_dividers() local
112 if (!clksel->reg) in rockchip_cpuclk_set_dividers()
116 __func__, clksel->reg, clksel->val); in rockchip_cpuclk_set_dividers()
117 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_dividers()
128 const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i]; in rockchip_cpuclk_set_pre_muxs() local
130 if (!clksel->reg) in rockchip_cpuclk_set_pre_muxs()
134 __func__, clksel->reg, clksel->val); in rockchip_cpuclk_set_pre_muxs()
135 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_pre_muxs()
146 const struct rockchip_cpuclk_clksel *clksel = &rate->post_muxs[i]; in rockchip_cpuclk_set_post_muxs() local
148 if (!clksel->reg) in rockchip_cpuclk_set_post_muxs()
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/OK3568_Linux_fs/kernel/drivers/clocksource/
H A Dtimer-cadence-ttc.c475 int clksel, ret; in ttc_timer_probe() local
503 clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); in ttc_timer_probe()
504 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_probe()
505 clk_cs = of_clk_get(timer, clksel); in ttc_timer_probe()
511 clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); in ttc_timer_probe()
512 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_probe()
513 clk_ce = of_clk_get(timer, clksel); in ttc_timer_probe()
/OK3568_Linux_fs/kernel/arch/mips/ralink/
H A Drt3883.c67 u32 clksel; in ralink_clk_init() local
71 clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) & in ralink_clk_init()
75 switch (clksel) { in ralink_clk_init()
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-qoriq.c57 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS]; member
827 u32 clksel; in mux_set_parent() local
832 clksel = hwc->parent_to_clksel[idx]; in mux_set_parent()
833 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); in mux_set_parent()
841 u32 clksel; in mux_get_parent() local
844 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in mux_get_parent()
846 ret = hwc->clksel_to_parent[clksel]; in mux_get_parent()
874 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) in get_pll_div()
877 pll = hwc->info->clksel[idx].pll; in get_pll_div()
878 div = hwc->info->clksel[idx].div; in get_pll_div()
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/OK3568_Linux_fs/kernel/arch/arm/mach-imx/
H A Dmach-imx6q.c170 u32 clksel; in imx6q_1588_init() local
195 clksel = clk_is_match(ptp_clk, enet_ref) ? in imx6q_1588_init()
202 clksel); in imx6q_1588_init()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/zte/
H A Dzx_vou.c138 u32 clksel; member
145 .clksel = VOU_CLK_GL0_SEL,
149 .clksel = VOU_CLK_GL1_SEL,
157 .clksel = VOU_CLK_VL0_SEL,
161 .clksel = VOU_CLK_VL1_SEL,
165 .clksel = VOU_CLK_VL2_SEL,
618 zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel, 0); in zx_vou_layer_enable()
622 zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel, in zx_vou_layer_enable()
623 bits->clksel); in zx_vou_layer_enable()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rcar-du/
H A Drcar_lvds.c192 u32 clksel; member
197 u32 clksel, bool dot_clock_only) in rcar_lvds_d3_e3_pll_calc() argument
305 pll->clksel = clksel; in rcar_lvds_d3_e3_pll_calc()
339 lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT in __rcar_lvds_pll_setup_d3_e3()
/OK3568_Linux_fs/kernel/drivers/mfd/
H A Dasic3.c387 unsigned long clksel = 0; in asic3_irq_probe() local
397 clksel |= CLOCK_SEL_CX; in asic3_irq_probe()
399 clksel); in asic3_irq_probe()
961 unsigned long clksel; in asic3_probe() local
990 clksel = 0; in asic3_probe()
991 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel); in asic3_probe()
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Des7243e.c325 u8 clksel = 0; in es7243e_set_dai_fmt()
331 es7243e_read(0x02, &clksel, i2c_clt[i]); //get spd interface in es7243e_set_dai_fmt()
371 clksel &= 0xfe; in es7243e_set_dai_fmt()
375 clksel |= 0x01; in es7243e_set_dai_fmt()
379 clksel |= 0x01; in es7243e_set_dai_fmt()
383 clksel &= 0xfe; in es7243e_set_dai_fmt()
390 es7243e_write(0x02, clksel, i2c_clt[i]); in es7243e_set_dai_fmt()
/OK3568_Linux_fs/u-boot/drivers/mmc/
H A Dsocfpga_dw_mmc.c84 host->clksel = socfpga_dwmci_clksel; in socfpga_dwmmc_ofdata_to_platdata()
H A Dexynos_dw_mmc.c119 host->clksel = exynos_dwmci_clksel; in exynos_dwmci_core_init()
H A Ddw_mmc.c776 if (host->clksel)
777 host->clksel(host);
/OK3568_Linux_fs/u-boot/include/
H A Ddwmmc.h185 void (*clksel)(struct dwmci_host *host); member
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-omap3/
H A Dcpu.h402 u32 clksel; /* 0xd40 */ member
/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/omap3/
H A Dclock.c614 clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel); in prcm_init()